Add support for the new DSI IP found in the Kompanio Ultra MT8196 SoC and its Dimensity and Genio variants.
Differently from the older DSI IPs, the one from MT8196 requires the initialization of all of the QoS parameters and can make use of a DSI SRAM reserved buffer (present also on older SoCs but not mandatory on those). Signed-off-by: AngeloGioacchino Del Regno <[email protected]> --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 + drivers/gpu/drm/mediatek/mtk_dsi.c | 67 ++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 08f6be311dd1..aec8da072a41 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -828,6 +828,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8189-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8196-dsi", + .data = (void *)MTK_DSI }, { } }; diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 16bf08bee38e..d930cb3c4d74 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -373,6 +373,59 @@ static const u16 mtk_dsi_regs_mt8186[DSI_ADV_REG_MAX] = { [DSI_CMDQ] = 0xd00, }; +static const u16 mtk_dsi_regs_main_v2[DSI_MAIN_REG_MAX] = { + [DSI_START] = 0x00, + [DSI_INTEN] = 0x08, + [DSI_INTSTA] = 0x0c, + [DSI_CON_CTRL] = 0x30, + [DSI_MODE_CTRL] = 0x34, + [DSI_TXRX_CTRL] = 0x38, + [DSI_PSCTRL] = 0x3c, + [DSI_VSA_NL] = 0x60, + [DSI_VBP_NL] = 0x64, + [DSI_VFP_NL] = 0x68, + [DSI_VACT_NL] = 0x6c, + [DSI_SIZE_CON] = 0x2c, + [DSI_HSA_WC] = 0x80, + [DSI_HBP_WC] = 0x84, + [DSI_HFP_WC] = 0x88, + [DSI_CMDQ_SIZE] = 0x44, + [DSI_HSTX_CKL_WC] = 0x100, + [DSI_RX_DATA0] = 0xa4, + [DSI_RX_DATA1] = 0xa8, + [DSI_RX_DATA2] = 0xac, + [DSI_RX_DATA3] = 0xb0, + [DSI_RACK] = 0xb4, + [DSI_PHY_LCCON] = 0x7d0, + [DSI_PHY_LD0CON] = 0x7d4, + [DSI_PHY_TIMECON0] = 0x600, + [DSI_PHY_TIMECON1] = 0x604, + [DSI_PHY_TIMECON2] = 0x608, + [DSI_PHY_TIMECON3] = 0x60c, +}; + +static const u16 mtk_dsi_regs_qos_v2[DSI_QOS_REG_MAX] = { + [DSI_QOS_BUF_CON0] = 0x300, + [DSI_QOS_BUF_CON1] = 0x304, + [DSI_QOS_TX_BUF_RW_TIMES] = 0x310, + [DSI_QOS_SODI_HIGH] = 0x314, + [DSI_QOS_SODI_LOW] = 0x318, + [DSI_QOS_PREULTRA_HIGH] = 0x324, + [DSI_QOS_PREULTRA_LOW] = 0x328, + [DSI_QOS_ULTRA_HIGH] = 0x32c, + [DSI_QOS_ULTRA_LOW] = 0x330, + [DSI_QOS_URGENT_HIGH] = 0x334, + [DSI_QOS_URGENT_LOW] = 0x338, + [DSI_QOS_PREURGENT_HIGH] = 0x33c +}; + +static const u16 mtk_dsi_regs_mt8196[DSI_ADV_REG_MAX] = { + [DSI_VM_CMD_CON] = 0x110, + [DSI_SHADOW_DEBUG] = 0xd0, + [DSI_CMDQ] = 0x400, + [DSI_VDE] = 0x3f8, +}; + static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b) { return container_of(b, struct mtk_dsi, bridge); @@ -1743,6 +1796,19 @@ static const struct mtk_dsi_driver_data mt8189_dsi_driver_data = { .support_per_frame_lp = true, }; +static const struct mtk_dsi_driver_data mt8196_dsi_driver_data = { + .reg_main = mtk_dsi_regs_main_v2, + .reg_qos = mtk_dsi_regs_qos_v2, + .reg_adv = mtk_dsi_regs_mt8196, + .max_link_rate_mbps = 2000, + .dsi_sram_bytes = 32, + .pixels_per_iter = 2, + .num_burst_lines = 8, + .has_size_ctl = true, + .cmdq_long_packet_ctl = true, + .support_per_frame_lp = true, +}; + static const struct of_device_id mtk_dsi_of_match[] = { { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data }, { .compatible = "mediatek,mt8167-dsi", .data = &mt2701_dsi_driver_data }, @@ -1751,6 +1817,7 @@ static const struct of_device_id mtk_dsi_of_match[] = { { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data }, { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data }, { .compatible = "mediatek,mt8189-dsi", .data = &mt8189_dsi_driver_data }, + { .compatible = "mediatek,mt8196-dsi", .data = &mt8196_dsi_driver_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_dsi_of_match); -- 2.55.0
