Re: [PATCH] drm/mediatek: mtk_hdmi_v2: fix VID_DOWNSAMPLE_CONFIG register offset

[AngeloGioacchino Del Regno]

On 8/28/26 14:10, Julien Stephan wrote:

According to the datasheet, VID_DOWNSAMPLE_CONFIG is at offset 0x8f0;
0x8d0 is the VID_CSC_COEFF_0 register.

Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188")
Signed-off-by: Julien Stephan <jstep...@baylibre.com>

Reviewed-by: AngeloGioacchino Del Regno 
<angelogioacchino.delre...@collabora.com>