On Fri, Sep 11, 2026 at 11:51:04AM +0300, YİĞİTCAN KAVAKLI via B4 Relay wrote: > From: YİĞİTCAN KAVAKLI <[email protected]> > > On Qualcomm SM6125 (Snapdragon 665 / Trinket DPU 5.4.0), calculating the > programmable prefetch start counter strictly as: > > (vert_total - vfp_fetch_lines) * horiz_total + 1 > > causes the fetch trigger to evaluate on the active-video to vertical > front porch line boundary. In hardware, this triggers an internal line > buffer FIFO conflict within the INTF timing generator, resulting in > immediate DSI FIFO overflow and timeout errors (status=5) and complete > loss of pixel output. > > Qualcomm downstream display drivers mitigate this erratum via > delay_prg_fetch_start = true, delaying the fetch start by one scanline > (+ horiz_total) into vertical front porch line 1. > > Introduce 'has_prg_fetch_delay' in struct dpu_caps, enable it for SM6125 > in its catalog entry, and throttle fetch start in programmable_fetch_config() > when the capability is set.
'has_foo' usually means that there is an optional feature. In your case it's more like 'needs_foo'. > > Signed-off-by: YİĞİTCAN KAVAKLI <[email protected]> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 + Fixes: 9b6f4fedaac2 ("drm/msm/dpu: Add SM6125 support") > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 +++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ > 3 files changed, 14 insertions(+) > > + /* > + * SM6125 (DPU 5.4 / Trinket) quirk matching downstream Drop the codename, please. > + * delay_prg_fetch_start = true. Throttle fetch start > + * to the second line after active video (VFP line 1). > + */ > + if (catalog && catalog->caps && > catalog->caps->has_prg_fetch_delay) > + vfp_fetch_start_vsync_counter += horiz_total; > + > f.enable = 1; > f.fetch_start = vfp_fetch_start_vsync_counter; > } > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index > f45faf87333e89bbd463504ae3219609ef6209bd..db3cbf9fa04a13baf3ac40390757ed24120ccccd > 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -273,6 +273,7 @@ struct dpu_rotation_cfg { > * @has_dim_layer dim layer feature status > * @has_idle_pc indicate if idle power collapse feature is supported > * @has_3d_merge indicate if 3D merge is supported > + * @has_prg_fetch_delay indicate if programmable fetch start requires a > 1-line delay > * @max_linewidth max linewidth for sspp > * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes > * @max_hdeci_exp max horizontal decimation supported (max is 2^value) > @@ -285,6 +286,7 @@ struct dpu_caps { > bool has_dim_layer; > bool has_idle_pc; > bool has_3d_merge; > + bool has_prg_fetch_delay; > /* SSPP limits */ > u32 max_linewidth; > u32 pixel_ram_size; > > -- > 2.47.3 > > -- With best wishes Dmitry
