Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] dt-bindings: mtk-wdma: incorrect mt8173 fallback for 34-bit IOVA SoCs --
commit 9abef195ff9795774aad1384f098d2674d2e411c Author: AngeloGioacchino Del Regno <[email protected]> dt-bindings: display: mediatek: wdma: Add compatibles for more SoCs This commit adds missing device tree compatible strings for the Write DMA hardware in multiple MediaTek SoCs, including MT6893, MT8183, MT8186, MT8192, and MT8195. It also specifies that MT6893 is not compatible with MT8173 due to its introduction of destination addresses larger than 32 bits. > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml > @@ -22,11 +22,16 @@ properties: > compatible: > oneOf: > - enum: > + - mediatek,mt6893-disp-wdma > - mediatek,mt8173-disp-wdma > - items: > - enum: > - mediatek,mt6795-disp-wdma > - mediatek,mt8167-disp-wdma > + - mediatek,mt8183-disp-wdma > + - mediatek,mt8186-disp-wdma > + - mediatek,mt8192-disp-wdma > + - mediatek,mt8195-disp-wdma > - const: mediatek,mt8173-disp-wdma [Severity: High] Does using the mediatek,mt8173-disp-wdma fallback for these newer SoCs risk silent DMA memory corruption or IOMMU translation faults when writing to addresses above 4GB? The WDMA hardware in MT8186, MT8192, and MT8195 uses 34-bit IOVA spaces, which is indicated by the IOVA_34_EN flag in their IOMMU platform data. When the DRM writeback driver configures the WDMA, it will be handed 34-bit dma_addr_t addresses. Because the schema specifies the MT8173 fallback, the driver binds using the MT8173 match data. Since MT8173 only supports 32-bit addresses, its driver data configures reg_wdma_dst_addr0_msb = 0. This causes the driver to write only the lower 32 bits of the destination address, silently dropping the upper 2 bits of the 34-bit IOVA during normal display writeback operations. -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=12
