> The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller, and > the rate they carry is ultimately produced by the HDMI PHY, which > registers hdmitx0_pixelclk as a clock provider. > > Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them > reaches that parent, instead of being clamped to whatever rate the > parent already happens to run at. > > Co-developed-by: Dominique Belhachemi <[email protected]> > Signed-off-by: Dominique Belhachemi <[email protected]> > Reviewed-by: Joshua Peisach <[email protected]> > Signed-off-by: Michal Wilczynski <[email protected]>
Sashiko has reviewed this patch and found no issues. It looks great! -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=14
