Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] dt-bindings: mfd: bus fault during PHY probe due to artificial node split --
commit 4723344ba643109500316c0b52d890ec9a27e43e Author: Michal Wilczynski <[email protected]> dt-bindings: mfd: Add starfive,jh7110-hdmi-subsystem Add the dt-binding for the StarFive JH7110 HDMI subsystem. The JH7110 HDMI IP is a monolithic block containing both the digital controller and analog PHY in a single register space. This binding defines the parent device, which holds the shared register map and populates its two children: the PHY and the controller. This is necessary to resolve a circular clock dependency between the HDMI block and the VOUT clock generator. > diff --git > a/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.yaml > b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.yaml > new file mode 100644 > index 0000000000000..18034d8273b86 > --- /dev/null > +++ > b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.yaml > @@ -0,0 +1,95 @@ [ ... ] > +properties: > + compatible: > + const: starfive,jh7110-hdmi-subsystem > + > + reg: > + maxItems: 1 > + > + phy: > + $ref: /schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml# > + > + controller: > + $ref: /schemas/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml# [Severity: High] Does this artificial split of a monolithic block into child nodes create a probe order issue? Because the controller depends on the phy (via clocks = <&hdmi_phy> in the example below), fw_devlink guarantees the phy driver probes first. During its probe, the phy driver calls clk_set_rate(inno->phyclk, 297000000), which accesses the shared register space via regmap. However, since the HDMI system clock (JH7110_VOUTCLK_HDMI_TX_SYS) is assigned exclusively to the controller child, it is not enabled during the phy probe. Will this unclocked access wedge the bus and cause a synchronous external abort when the phy accesses the shared register window? > + > +required: > + - compatible > + - reg > + - phy > + - controller > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/starfive,jh7110-crg.h> > + #include <dt-bindings/reset/starfive,jh7110-crg.h> > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + > + hdmi@29590000 { > + compatible = "starfive,jh7110-hdmi-subsystem"; > + reg = <0x29590000 0x4000>; > + > + controller { > + compatible = "starfive,jh7110-inno-hdmi-controller"; > + clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, > + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, > + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, > + <&hdmi_phy>; [ ... ] > + hdmi_phy: phy { > + compatible = "starfive,jh7110-inno-hdmi-phy"; > + #clock-cells = <0>; > + clocks = <&xin24m>; > + #phy-cells = <0>; > + }; > + }; > + }; > +... -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=3
