Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] drm/msm: hardware corruption due to zero-initialized LM3 base address --
commit f01ed8464ded4b4b827835f9551a26ed60e5dded Author: Muzaffer Kadir <[email protected]> drm: msm: mdp5: Add MDP5 configuration for MSM8952 This commit adds the mdp5_cfg_hw entry for MDP5 version v1.12 found on the MSM8952. > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c > index 7c91fc1915f39..d34c94d6f7e2e 100644 > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c > @@ -744,6 +744,86 @@ static const struct mdp5_cfg_hw msm8x76_config = { > .max_clk = 360000000, > }; > > +static const struct mdp5_cfg_hw msm8952_config = { > + .name = "msm8952", [ ... ] > + .lm = { > + .count = 2, > + .base = { 0x44000, 0x47000 }, > + .instances = { > + { .id = 0, .pp = 0, .dspp = 0, > + .caps = MDP_LM_CAP_DISPLAY, }, > + { .id = 3, .pp = -1, .dspp = -1, > + .caps = MDP_LM_CAP_WB }, > + }, [Severity: High] Will this lead to hardware register corruption when LM3 is brought up? In msm8952_config, the .lm.base array is initialized sequentially as { 0x44000, 0x47000 }, which assigns base[0] = 0x44000 and base[1] = 0x47000. This leaves base[3] implicitly zero-initialized. However, the second LM instance is defined with .id = 3 (for LM3). When the driver configures this mixer, it uses lm->id to access the LM registers. Because base[3] is 0, the driver will mistakenly perform writes to offset 0x0 of the MDP block (which corresponds to top-level registers). Should designated initializers be used for the base array here, such as { [0] = 0x44000, [3] = 0x47000 }? > + .nb_stages = 8, > + .max_width = 2048, > + .max_height = 0xFFFF, > + }, -- Sashiko AI review ยท https://sashiko.dev/#/patchset/20260916-msm8952-initial-support-v2-0-798c2602d...@mainlining.org?part=13
