Icenowy Zheng 於 2026/9/18 下午 06:50 寫道:
在 2026-09-18五的 11:01 +0800,Joey Lu写道:
Add the Nuvoton MA35D1 DCUltraLite (nuvoton,ma35d1-dcu) to the
binding.
The DCUltraLite uses only four clocks (core, axi, ahb, pix0) and one
reset (core), with a single output port.

The MA35D1 clock controller gates the core, AXI and AHB clocks with a
single bit, but each remains a distinct clock line feeding the IP
with
its own rate constraints, so all four must still be listed
individually
in the devicetree; core, axi and ahb happen to share the same clock
phandle.

Move the clocks/clock-names minItems to 4 and resets/reset-names
minItems to 1 at the top level, since that is the lowest count any
supported variant needs.  Add an allOf/if block that tightens the
constraint back up to the fixed 5-clock/3-reset topology required by
the existing thead,th1520-dc8200 compatible, and another one that
caps
the new nuvoton,ma35d1-dcu compatible at the 4-clock/1-reset count it
actually wires up.

Restrict the same nuvoton,ma35d1-dcu if block to a single port@0,
since the DCUltraLite only has one output port.
By the way, when will the MA35D1 device tree sources be updated? I saw
a lot of drivers being merged but w/o corresponding DT nodes: sdhci-of-
ma35d1, nuvoton-ma35d1-nand-controller, phy-ma35d1-usb2, rtc-ma35d1,
spi-ma35d1-qspi, ma35d1_wdt.

Thanks,
Icenowy
We are currently reviewing several peripheral device tree updates, including USB/PHY, CAN, and other related blocks.

Once the core driver support is in place, we plan to do a more thorough review and update of the MA35D1 device tree sources to ensure the corresponding DT nodes are properly added and aligned with the upstream drivers.

Thanks for your patience and feedback.
Signed-off-by: Joey Lu <[email protected]>
Acked-by: Conor Dooley <[email protected]>
---
  .../bindings/display/verisilicon,dc.yaml      | 51
+++++++++++++++++++
  1 file changed, 51 insertions(+)

diff --git
a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
index 919a900122012..e1e6a3a953646 100644
--- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
+++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
@@ -17,6 +17,7 @@ properties:
      items:
        - enum:
            - thead,th1520-dc8200
+          - nuvoton,ma35d1-dcu
        - const: verisilicon,dc # DC IPs have discoverable ID/revision
registers
   reg:
@@ -26,6 +27,7 @@ properties:
      maxItems: 1
   clocks:
+    minItems: 4
      items:
        - description: DC Core clock
        - description: DMA AXI bus clock
@@ -34,6 +36,7 @@ properties:
        - description: Pixel clock of output 1
   clock-names:
+    minItems: 4
      items:
        - const: core
        - const: axi
@@ -42,12 +45,14 @@ properties:
        - const: pix1
   resets:
+    minItems: 1
      items:
        - description: DC Core reset
        - description: DMA AXI bus reset
        - description: Configuration AHB bus reset
   reset-names:
+    minItems: 1
      items:
        - const: core
        - const: axi
@@ -79,6 +84,52 @@ required:
    - reset-names
    - ports
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: thead,th1520-dc8200
+    then:
+      properties:
+        clocks:
+          minItems: 5
+
+        clock-names:
+          minItems: 5
+
+        resets:
+          minItems: 3
+
+        reset-names:
+          minItems: 3
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nuvoton,ma35d1-dcu
+    then:
+      properties:
+        clocks:
+          maxItems: 4
+
+        clock-names:
+          maxItems: 4
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          maxItems: 1
+
+        ports:
+          properties:
+            port@1: false
+
+          required:
+            - port@0
+
  additionalProperties: false
 examples:

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