From: Muzaffer Kadir <[email protected]> Add initial support for MSM8952 SoC.
AI help is used for calculating qfprom nodes. Downstream reference for port is [1] which is very lightly modified version of [2]. Downstream reference used to calculate qfprom: [3] Currently supported features in this port: - Internal Storage support - MDSS - Basic Adsp remote proc support - Blsp 1 and 2 with all i2c and spi - Tsens support - USB - RPM with mpm and master-stats [1] https://github.com/Asderdd/android_kernel_generalmobile_shamrock/blob/cm-14.1/arch/arm/boot/dts/qcom/msm8952.dtsi [2] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wear-7.0.0_r0.3/arch/arm/boot/dts/qcom/msm8952.dtsi [3] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wear-7.0.0_r0.3/drivers/thermal/msm-tsens.c#1621 Assisted-by: LLM Signed-off-by: Muzaffer Kadir <[email protected]> --- arch/arm64/boot/dts/qcom/msm8952.dtsi | 2696 +++++++++++++++++++++++++++++++++ 1 file changed, 2696 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8952.dtsi b/arch/arm64/boot/dts/qcom/msm8952.dtsi new file mode 100644 index 000000000000..fa343271a024 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8952.dtsi @@ -0,0 +1,2696 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2026 Muzaffer Kadir <[email protected]> + * + * Based on msm8937.dtsi: + * Copyright (c) 2023, Dang Huynh <[email protected]> + * adapted with data from msm8952.dtsi and msm8952-*.dtsi files in Qualcomm's msm-3.10 release + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> +#include <dt-bindings/clock/qcom,gcc-msm8952.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/arm/qcom,ids.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + clocks = <&apcs0>; + #cooling-cells = <2>; + qcom,acc = <&acc0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + clocks = <&apcs0>; + #cooling-cells = <2>; + qcom,acc = <&acc1>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + clocks = <&apcs0>; + #cooling-cells = <2>; + qcom,acc = <&acc2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + clocks = <&apcs0>; + #cooling-cells = <2>; + qcom,acc = <&acc3>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + clocks = <&apcs1>; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + qcom,acc = <&acc4>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + clocks = <&apcs1>; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + qcom,acc = <&acc5>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + clocks = <&apcs1>; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + qcom,acc = <&acc6>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + clocks = <&apcs1>; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + qcom,acc = <&acc7>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8952", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", + "bus", + "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + qseecom_mem: reserved@85b00000 { + reg = <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg = <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: mpss@86c00000 { + reg = <0x0 0x86c00000 0x0 0x5600000>; + no-map; + }; + + adsp_mem: adsp@8c200000 { + reg = <0x0 0x8c200000 0x0 0x1700000>; + no-map; + }; + + rmtfs_mem: rmtfs { + compatible = "qcom,rmtfs-mem"; + + size = <0x0 0x200000>; + alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; + no-map; + + qcom,client-id = <1>; + }; + + ramoops_mem: ramoops@dffc0000 { + compatible = "ramoops"; + reg = <0x0 0xdffc0000 0x0 0x40000>; + + record-size = <0x10000>; + console-size = <0x10000>; + pmsg-size = <0x20000>; + + status = "disabled"; + }; + + mba_mem: mba { + size = <0x0 0x100000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status = "disabled"; + }; + + venus_mem: venus { + size = <0x0 0x500000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status = "disabled"; + }; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm: remoteproc { + compatible = "qcom,msm8952-rpm-proc", "qcom,rpm-proc"; + + master-stats { + compatible = "qcom,rpm-master-stats"; + qcom,rpm-msg-ram = <&apss_master_stats>, + <&mpss_master_stats>, + <&pronto_master_stats>, + <&tz_master_stats>, + <&lpass_master_stats>; + qcom,master-names = "APSS", + "MPSS", + "PRONTO", + "TZ", + "LPASS"; + }; + + smd-edge { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs1 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8952", "qcom,smd-rpm"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8952", + "qcom,rpmcc-msm8976", + "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8952-rpmpd", + "qcom,msm8917-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + }; + }; + }; + }; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + + interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs1 1>; + interrupt-controller; + #interrupt-cells = <2>; + #power-domain-cells = <0>; + interrupt-parent = <&intc>; + qcom,rpm-msg-ram = <&apss_mpm>; + qcom,mpm-pin-count = <64>; + qcom,mpm-pin-map = <2 184>, /* TSENS UPLOW */ + <49 140>, /* USB ASYNC */ + <53 72>, /* MDSS */ + <58 134>, /* USB */ + <62 190>; /* SPMI */ + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs1 10>; + qcom,smem = <443>, <429>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells = <2>; + + qcom,entry-name = "slave-kernel"; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs1 14>; + qcom,smem = <435>, <428>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells = <2>; + qcom,entry-name = "slave-kernel"; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + + interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs1 18>; + qcom,smem = <451>, <431>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells = <2>; + + qcom,entry-name = "slave-kernel"; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + mboxes = <0>, <&apcs1 13>, <&apcs1 9>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + qfprom: qfprom@5c000 { + compatible = "qcom,msm8952-qfprom", "qcom,qfprom"; + reg = <0x0005c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base0: base0@a0 { + reg = <0xa0 0x1>; + bits = <0 8>; + }; + + tsens_s5_p1: s5-p1@a1 { + reg = <0xa1 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@a1 { + reg = <0xa1 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@a2 { + reg = <0xa2 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@a3 { + reg = <0xa3 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@a4 { + reg = <0xa4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@a4 { + reg = <0xa4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@a5 { + reg = <0xa5 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@a6 { + reg = <0xa6 0x1>; + bits = <2 6>; + }; + + tsens_base1: base1@a7 { + reg = <0xa7 0x1>; + bits = <0 8>; + }; + + tsens_mode: mode@d0 { + reg = <0xd0 0x1>; + bits = <0 3>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <3 6>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg = <0xd1 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@d1 { + reg = <0xd1 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@d4 { + reg = <0xd4 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@d5 { + reg = <0xd5 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@d6 { + reg = <0xd6 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@d7 { + reg = <0xd7 0x1>; + bits = <1 6>; + }; + + tsens_s9_p1: s9-p1@f0 { + reg = <0xf0 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@f0 { + reg = <0xf0 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1: s10-p1@f1 { + reg = <0xf1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10-p2@f2 { + reg = <0xf2 0x1>; + bits = <2 6>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram", "mmio-sram"; + reg = <0x00060000 0x8000>; + + ranges = <0 0x00060000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + + apss_master_stats: sram@150 { + reg = <0x150 0x14>; + }; + + apss_mpm: sram@1d0 { + reg = <0x1d0 0x64>; + }; + + mpss_master_stats: sram@1150 { + reg = <0x1150 0x14>; + }; + + pronto_master_stats: sram@2550 { + reg = <0x2550 0x14>; + }; + + tz_master_stats: sram@3550 { + reg = <0x3550 0x14>; + }; + + lpass_master_stats: sram@4550 { + reg = <0x4550 0x14>; + }; + }; + + usb_hs_phy: phy@6c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0006c000 0x200>; + #phy-cells = <0>; + clocks = <&xo_board>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", + "ahb", + "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + + status = "disabled"; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8952-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, <&tsens_base1>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <11>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + crypto_dma: dma-controller@704000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + num-channels = <16>; + qcom,ee = <1>; + qcom,num-ees = <4>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible = "qcom,crypto-v5.4"; + reg = <0x0073a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", + "bus", + "core"; + dmas = <&crypto_dma 2>, <&crypto_dma 3>; + dma-names = "rx", "tx"; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8952-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + wakeup-parent = <&mpm>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1_uart1_console_default: blsp1-uart1-console-default-state { + rx-pins { + pins = "gpio1"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + + tx-pins { + pins = "gpio0"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + }; + + blsp1_uart1_console_sleep: blsp1-uart1-console-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c1_default: blsp1-i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + cs-pins { + pins = "gpio2"; + function = "blsp_spi1"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp1_spi1_sleep: blsp1-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi2_default: blsp1-spi2-default-state { + cs-pins { + pins = "gpio6"; + function = "blsp_spi2"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp1_spi2_sleep: blsp1-spi2-sleep-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + cs-pins { + pins = "gpio10"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp1_spi3_sleep: blsp1-spi3-sleep-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi4_default: blsp1-spi4-default-state { + cs-pins { + pins = "gpio14"; + function = "blsp_spi4"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp1_spi4_sleep: blsp1-spi4-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_spi1_default: blsp2-spi1-default-state { + cs-pins { + pins = "gpio18"; + function = "blsp_spi5"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp2_spi1_sleep: blsp2-spi1-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c2_default: blsp2-i2c2-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + cs-pins { + pins = "gpio22"; + function = "blsp_spi6"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp2_spi2_sleep: blsp2-spi2-sleep-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c3_default: blsp2-i2c3-default-state { + pins = "gpio94", "gpio95"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { + pins = "gpio94", "gpio95"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_spi3_default: blsp2-spi3-default-state { + cs-pins { + pins = "gpio94"; + function = "blsp_spi7"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins = "gpio92", "gpio93", "gpio95"; + function = "blsp_spi7"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp2_spi3_sleep: blsp2-spi3-sleep-state { + pins = "gpio92", "gpio93", "gpio94", "gpio95"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c4_default: blsp2-i2c4-default-state { + pins = "gpio98", "gpio99"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { + pins = "gpio98", "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_spi4_default: blsp2-spi4-default-state { + cs-pins { + pins = "gpio98"; + function = "blsp_spi8"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins = "gpio96", "gpio97", "gpio99"; + function = "blsp_spi8"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp2_spi4_sleep: blsp2-spi4-sleep-state { + pins = "gpio96", "gpio97", "gpio98", "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + sdc2_cmd_default: cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + sdc2_data_default: data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8952"; + reg = <0x01800000 0x80000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8952", "syscon"; + reg = <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + reg = <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names = "mdss_phys", + "vbif_phys"; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&gcc GCC_MDSS_BCR>; + + status = "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,msm8952-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + iommus = <&apps_iommu 0x17>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-266670000 { + opp-hz = /bits/ 64 <266670000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@1a98000 { + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x01a98000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmpd RPMPD_VDDCX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible = "qcom,adreno-405.0", "qcom,adreno"; + reg = <0x01c00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + clock-names = "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + power-domains = <&gcc OXILI_GX_GDSC>; + operating-points-v2 = <&opp_table>; + iommus = <&gpu_iommu 0>, <&gpu_iommu 1>; + #cooling-cells = <2>; + + status = "disabled"; + + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmpd_opp_nom_plus>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + apps_iommu: iommu@1e20000 { + compatible = "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + qcom,iommu-secure-id = <17>; + + /* CPP */ + iommu-ctx@13000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x13000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* JPEG ENC0 */ + iommu-ctx@14000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x14000 0x1000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* VFE */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x15000 0x1000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x16000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x17000 0x1000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* PRONTO */ + iommu-ctx@18000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x18000 0x1000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01f08000 0x10000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + qcom,iommu-secure-id = <18>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x0 0x1000>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + qcom,ctx-asid = <0>; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + qcom,ctx-asid = <2>; + }; + + /* gfx3d priv */ + iommu-ctx@3000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + qcom,ctx-asid = <1>; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&mpm 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + qcom,ee = <0>; + qcom,channel = <0>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x04044000 0x19000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + + num-channels = <6>; + qcom,ee = <0>; + qcom,num-ees = <1>; + qcom,powered-remotely; + + status = "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible = "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x500>, <0x07824000 0x800>, <0x7824e00 0x200>; + reg-names = "hc", "core", "cqhci"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + + resets = <&gcc GCC_SDCC1_BCR>; + + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd RPMPD_VDDCX>; + + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + + status = "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible = "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc", "core"; + + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + + resets = <&gcc GCC_SDCC2_BCR>; + + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd RPMPD_VDDCX>; + + bus-width = <4>; + + status = "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1f000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + num-channels = <12>; + qcom,num-ees = <4>; + qcom,ee = <0>; + qcom,controlled-remotely; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_uart1_console_default>; + pinctrl-1 = <&blsp1_uart1_console_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + }; + + blsp1_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_i2c1_default>; + pinctrl-1 = <&blsp1_i2c1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_spi2_default>; + pinctrl-1 = <&blsp1_spi2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_spi3_default>; + pinctrl-1 = <&blsp1_spi3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_i2c4_default>; + pinctrl-1 = <&blsp1_i2c4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_spi4: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_spi4_default>; + pinctrl-1 = <&blsp1_spi4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + usb_dma: dma-controller@78c4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x078c4000 0x17000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + num-channels = <4>; + qcom,num-ees = <4>; + qcom,ee = <0>; + qcom,controlled-remotely; + }; + + usb: usb@78db000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts-extended = <&mpm 58 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", + "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + dr_mode = "otg"; + phy_type = "ulpi"; + phys = <&usb_hs_phy>; + phy-names = "usb-phy"; + #reset-cells = <1>; + + status = "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x1f000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_spi1: spi@7af5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_spi1_default>; + pinctrl-1 = <&blsp2_spi1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_i2c2: i2c@7af6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af6000 0x600>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_spi2: spi@7af6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af6000 0x600>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_spi2_default>; + pinctrl-1 = <&blsp2_spi2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_i2c3: i2c@7af7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af7000 0x600>; + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_i2c3_default>; + pinctrl-1 = <&blsp2_i2c3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_spi3: spi@7af7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af7000 0x600>; + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_spi3_default>; + pinctrl-1 = <&blsp2_spi3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_i2c4: i2c@7af8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af8000 0x600>; + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_i2c4_default>; + pinctrl-1 = <&blsp2_i2c4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_spi4: spi@7af8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af8000 0x600>; + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp2_spi4_default>; + pinctrl-1 = <&blsp2_spi4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + imem: sram@8600000 { + compatible = "qcom,msm8976-imem", + "syscon", "simple-mfd"; + reg = <0x08600000 0x1000>; + + ranges = <0 0x08600000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apcs1: mailbox@b011000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&a53pll_c1>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", + "aux", + "ref"; + #clock-cells = <0>; + }; + + a53pll_c1: clock@b016000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b016000 0x40>; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <0>; + operating-points-v2 = <&pll_opp_table_c1>; + + pll_opp_table_c1: opp-table { + compatible = "operating-points-v2"; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + }; + }; + }; + + watchdog@b017000 { + compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg = <0x0b017000 0x1000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; + clocks = <&sleep_clk>; + }; + + acc4: clock-controller@b088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b088000 0x1000>; + }; + + acc5: clock-controller@b098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b098000 0x1000>; + }; + + acc6: clock-controller@b0a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0a8000 0x1000>; + }; + + acc7: clock-controller@b0b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0b8000 0x1000>; + }; + + apcs0: mailbox@b111000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b111000 0x1000>; + #mbox-cells = <1>; + clocks = <&a53pll_c0>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", + "aux", + "ref"; + #clock-cells = <0>; + }; + + a53pll_c0: clock@b116000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b116000 0x40>; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <0>; + operating-points-v2 = <&pll_opp_table_c0>; + + pll_opp_table_c0: opp-table { + compatible = "operating-points-v2"; + + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <19200000>; + + frame@b121000 { + reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <2>; + + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + + status = "disabled"; + }; + }; + + acc0: clock-controller@b188000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b188000 0x1000>; + }; + + acc1: clock-controller@b198000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b198000 0x1000>; + }; + + acc2: clock-controller@b1a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1a8000 0x1000>; + }; + + acc3: clock-controller@b1b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1b8000 0x1000>; + }; + + a53pll_cci: clock@b1d0000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b1d0000 0x40>; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b1d1000 0x1000>; + clocks = <&a53pll_cci>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", + "aux", + "ref"; + #clock-cells = <0>; + #mbox-cells = <1>; + }; + + adsp: remoteproc@c200000 { + compatible = "qcom,msm8996-adsp-pil"; + reg = <0x0c200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_BB_CLK1>; + clock-names = "xo"; + + power-domains = <&rpmpd RPMPD_VDDCX>; + power-domain-names = "cx"; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs1 8>; + + qcom,smd-edge = <1>; + qcom,remote-pid = <2>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 1>; + + trips { + modem_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + qdsp-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 2>; + + trips { + qdsp_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + l2-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 4>; + + trips { + l2_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + + l2_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + + l2_crit: l2-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 5>; + + cooling-maps { + map0 { + trip = <&cpu4_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 6>; + + cooling-maps { + map0 { + trip = <&cpu5_alert1>; + cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 7>; + + cooling-maps { + map0 { + trip = <&cpu6_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 8>; + + cooling-maps { + map0 { + trip = <&cpu7_alert1>; + cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu0-3-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 9>; + + cooling-maps { + map0 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu0_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 10>; + + trips { + gpu_crit: gpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <19200000>; + }; +}; -- 2.55.0
