On Tue, 22 Sep 2026, Xiao Lu <[email protected]> wrote: > v2: Send the two related patches together as a series, as requested > by Jani. No code changes from v1.
I bounced this series to [email protected] as well, since the display code is shared with xe, and we want to run xe CI on it too. MAINTAINERS should indicate this. For future reference, please send Intel display patches to both intel-xe and intel-gfx mailing lists. Thanks, Jani. > > This series fixes two related issues in MST payload bandwidth > accounting that together caused 4K@60Hz to fail alongside two > 1080p@60Hz displays in a 3-display MST daisy-chain topology > (PS8650 hub -> ViewSonic VP2468 x2 -> Lenovo Pro 27UD-10). > > Patch 1 fixes the PBN value passed in the ALLOCATE_PAYLOAD sideband > request. The driver was using a TU-aligned PBN (e.g. 537) instead of > the actual video stream bandwidth (e.g. 496 for [email protected]), > inflating the requested PBN and causing -ENOSPC failures for > configurations that should fit within the available link bandwidth. > > Patch 2 tracks the allocated_pbn returned in the ALLOCATE_PAYLOAD > reply, and uses it alongside @pbn for bandwidth limit checks. This > ensures that any per-hop capacity constraints from intermediate MST > branches are correctly reflected in the source-side bandwidth check. > > Xiao Lu (2): > drm/i915/dp: fix PBN in ALLOCATE_PAYLOAD request to use actual video > bandwidth > drm/dp/mst: track allocated_pbn from ALLOCATE_PAYLOAD reply > > drivers/gpu/drm/display/drm_dp_mst_topology.c | 24 ++++++++++++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 +++++++++++------ > include/drm/display/drm_dp_mst_helper.h | 10 +++++++ > 3 files changed, 46 insertions(+), 12 deletions(-) -- Jani Nikula, Intel
