Julien Stephan <[email protected]> 於 2026年8月28日週五 下午8:10寫道： > > According to the datasheet, VID_DOWNSAMPLE_CONFIG is at offset 0x8f0; > 0x8d0 is the VID_CSC_COEFF_0 register.
Applied to mediatek-drm-fixes [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes Regards, Chun-Kuang. > > Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188") > Signed-off-by: Julien Stephan <[email protected]> > --- > drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h > b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h > index 521b35c7e14d..bf3ebf5492d1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h > @@ -173,7 +173,7 @@ > #define TPI_AUDIO_LOOKUP_EN BIT(2) > > /* Video downsampling configuration */ > -#define VID_DOWNSAMPLE_CONFIG 0x8d0 > +#define VID_DOWNSAMPLE_CONFIG 0x8f0 > #define C444_C422_CONFIG_ENABLE BIT(0) > #define C422_C420_CONFIG_ENABLE BIT(4) > #define C422_C420_CONFIG_BYPASS BIT(5) > > --- > base-commit: 1b78070aaef63512688aebfbc82365ef9d6660f1 > change-id: 20260828-mtk-hdmi-v2-fix-register-offset-879afc38cad1 > > Best regards, > -- > Julien Stephan <[email protected]> >
