Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] drm/msm: AB-BA deadlock between mode_config.mutex and plugged_lock --
commit 44822203f1a87c392f32673917903210fbaa2c96 Author: Yongxing Mou <[email protected]> drm/msm/dp: mark the SST connector disconnected when MST is enabled This patch updates the SST connector state to disconnected immediately after MST is initialized. This prevents the polling logic from observing a transient connected-to-disconnected transition and generating an unnecessary hotplug event. > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c > b/drivers/gpu/drm/msm/dp/dp_display.c > index 0e8181932c27d..327777f5c95e6 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -290,6 +290,10 @@ static void msm_dp_display_mst_enable(struct > msm_dp_display_private *dp) > } > > msm_dp->mst_active = true; > + > + scoped_guard(mutex, &msm_dp->connector->dev->mode_config.mutex) > + msm_dp->connector->status = connector_status_disconnected; [Severity: High] Does this introduce an AB-BA deadlock between mode_config.mutex and plugged_lock? When a DP MST monitor is hotplugged, the hotplug handler acquires plugged_lock first and eventually calls down to msm_dp_display_mst_enable(), which acquires mode_config.mutex here: msm_dp_hpd_plug_handle() guard(mutex)(&dp->plugged_lock); ... msm_dp_display_process_hpd_high(dp); msm_dp_display_mst_enable() scoped_guard(mutex, &msm_dp->connector->dev->mode_config.mutex) However, concurrently, the DRM subsystem probes display modes and holds mode_config.mutex prior to calling the connector's detect callback. The detect callback then attempts to acquire plugged_lock: drm_helper_probe_single_connector_modes() ... (holds mode_config.mutex) msm_dp_bridge_detect() guard(mutex)(&priv->plugged_lock); Can this lock inversion deadlock the system when DP MST monitors are plugged in? > + > msm_dp_mst_display_set_mgr_state(msm_dp, true); > } > -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=32
