On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote: > The AUX_LESS_WAKE_TIME bitfield in ALPM_CTL is widened from 6 bits to > 8 bits starting from xe3lpd (display version 35). Add the register > mask > and field macro for the wider bitfield and program the wake time > using > the appropriate macro based on the display version. > > v2: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd. [Suraj] > v3: Separate out AUX_LESS_WAKE_TIME bitfield change into its own > patch. [Jouni] > > Bspec: 71477 > Cc: Jouni Högander <[email protected]> > Signed-off-by: Animesh Manna <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_alpm.c | 8 ++++++-- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++ > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c > b/drivers/gpu/drm/i915/display/intel_alpm.c > index 924fa8dd4638..dc025058a626 100644 > --- a/drivers/gpu/drm/i915/display/intel_alpm.c > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c > @@ -610,8 +610,12 @@ static void lnl_alpm_configure(struct intel_dp > *intel_dp, > if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { > alpm_ctl = ALPM_CTL_ALPM_ENABLE | > ALPM_CTL_ALPM_AUX_LESS_ENABLE | > - ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS > | > - ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state- > >alpm_state.aux_less_wake_lines); > + ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS > ; > + > + if (DISPLAY_VER(display) < 35) > + alpm_ctl |= > ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state- > >alpm_state.aux_less_wake_lines); > + else > + alpm_ctl |= > ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(crtc_state- > >alpm_state.aux_less_wake_lines);
You should modify _lnl_compute_aux_less_wake_time to take this change into account. BR, Jouni Högander > > if (intel_dp->as_sdp_supported) > intel_alpm_configure_pr_as_sdp(intel_dp, > crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index bb577e7e3bbd..016ce24944dc 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -301,7 +301,9 @@ > #define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 > #define > ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) > REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK,(lines)-ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) > #define > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) > +#define > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD REG_GENMASK(7, 0) > #define > ALPM_CTL_AUX_LESS_WAKE_TIME(val) > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK,val) > +#define > ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(val) > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD,val) > > #define _ALPM_CTL2_A 0x60954 > #define ALPM_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, > _ALPM_CTL2_A)
