The display controller in Tegra20/30 SoCs features an 8-bit SPI interface
that closely resembles the MIPI DBI Type B protocol and is referred to as
'8-bit CPU'.
Add DC parametrization options needed for fine tuning by bridges.
Add 8-bit CPU interface in form of a bridge linking to RGB port.
Add 2 DBI Type B panels used in LG Optimus 2X which work with
the 8-bit CPU interface.
Svyatoslav Ryhel (6):
drm/tegra: dc: Expand available registers layouts
drm/tegra: rgb: Parameterize configuration based on bus flags
dt-bindings: display: tegra: Document 8-bit CPU parallel interface
drm/tegra: Add support for 8-bit CPU interface
dt-bindings: display: panel: Document Hitachi TX10D07VM0BAA and LG
LH400WV3 panels
drm/panel: Add Hitachi TX10D07VM0BAA and LG LH400WV3-SD04 MIPI DBI
panel driver
.../display/panel/hit,tx10d07vm0baa.yaml | 55 +++
.../display/tegra/nvidia,tegra-8bit-cpu.yaml | 138 ++++++
drivers/gpu/drm/panel/Kconfig | 14 +
drivers/gpu/drm/panel/Makefile | 1 +
.../drm/panel/panel-hitachi-tx10d07vm0baa.c | 396 ++++++++++++++++
drivers/gpu/drm/tegra/Kconfig | 7 +
drivers/gpu/drm/tegra/Makefile | 1 +
drivers/gpu/drm/tegra/cpu-bridge.c | 427 ++++++++++++++++++
drivers/gpu/drm/tegra/dc.c | 3 +-
drivers/gpu/drm/tegra/dc.h | 54 ++-
drivers/gpu/drm/tegra/rgb.c | 36 +-
11 files changed, 1121 insertions(+), 11 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/panel/hit,tx10d07vm0baa.yaml
create mode 100644
Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
create mode 100644 drivers/gpu/drm/panel/panel-hitachi-tx10d07vm0baa.c
create mode 100644 drivers/gpu/drm/tegra/cpu-bridge.c
--
2.53.0
