On Tue, Sep 29, 2026 at 3:27 AM Icenowy Zheng <[email protected]> wrote: > > 在 2026-09-28一的 01:21 -0400，Dominique Belhachemi写道： > > On Fri, Sep 11, 2026 at 11:33 AM Icenowy Zheng > > <[email protected]> wrote: > > > > > > I am still thinking how to decide whether to use dirty-tracking- > > > based > > > cache coherent maintenance or writecombine/uncached mapping. > > > > > Hi Icenowy, > > > > I looked into this again and writecombine/uncached mapping is the way > > to go. > > I think drm/imagination really requires it (because the correspoding > userspace driver advertises only one memory type with > `HOST_COHERENT_BIT` set), however in the future it could also add cache > maintenance support for performance reasons. > > > I used Bo Gan's XPbmtUC series and Michal Wilczynski's jh7110 display > > series and finally got the integrated BXE-4-32 GPU to work. > > The XPbmtUC series is problematic -- it "supports EIC7700" "with a > hypervisor", which means it cannot run on EIC7700 natively. This > severely restricts its usage. > > Samuel Holland from SiFive is working on patching the PTE on-the-fly, > but that will change all code accessing PTE in the kernel and thus is a > heavy work. > > P.S. For the JH7110 rascal+dust power issue, I did a try-and-error hack > at [1]. The basical register definition of this register (called > RGX_CR_POWER_EVENT) is available in their KM volcanic part (but it > seems to apply for rogue too), but the individual bits for domains are > undocumented, and the highest 8-bit seems to be some kind of multi-core > mask on Rogue. > > > [1] > https://github.com/Icenowy/linux/commit/09db317c9c229ef359e35463f8c08efd3e23c685 > Wow, thanks for sharing this. It works reliably and helped me get rid of the double-insmod for powervr. I integrated it into my branch with updated #defines.
Best -Dominique > > > > https://lore.kernel.org/all/[email protected]/ > > https://lore.kernel.org/all/[email protected]/ > > https://github.com/domibel/visionfive2_gpu_bringup > >
