On MT8188 the GPU timestamp counter reads zero until a register in the MFG configuration block routes the SoC system timer to it, and the setting is lost whenever the GPU power domain is turned off. As a result, the SYSTEM_TIMESTAMP query and the timestamps written by jobs are always zero, which breaks timestamp queries in userspace drivers.
This series adds an optional mediatek,mfgcfg phandle to the Mali binding, uses it in panfrost to set the register on every power-up, and adds it to the MT8188 GPU node. Without the phandle the driver behaves as before. MT8370 shares the GPU node and the MFG block with MT8188, so the binding allows the phandle there too, but the driver only enables the quirk on MT8188, where it was tested. Patch 3 is meant for the MediaTek tree; patches 1 and 2 can go through drm-misc. Tested on the Lenovo Chromebook Duet Gen 9 (Ciri, MT8188): the 13 MHz counter advances by 100 ms over a 100 ms sleep, also after resuming from deep suspend. Michał Kopeć (3): dt-bindings: gpu: mali-bifrost: Add the MT8188 MFGCFG phandle drm/panfrost: Enable the GPU timestamp counter on MT8188 arm64: dts: mediatek: mt8188: Add the MFGCFG phandle to the GPU .../bindings/gpu/arm,mali-bifrost.yaml | 17 ++++++++ arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1 + drivers/gpu/drm/panfrost/panfrost_device.h | 1 + drivers/gpu/drm/panfrost/panfrost_drv.c | 1 + drivers/gpu/drm/panfrost/panfrost_gpu.c | 39 +++++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_gpu.h | 1 + 6 files changed, 60 insertions(+) base-commit: 70456f05d4b6396b22048c4b8cd3cb98ecf9f9e3 -- 2.55.0
