On Mon, Oct 05, 2026 at 12:54:28PM +0530, Balaji Kalkonda wrote:
> Add device node for the DisplayPort controller, its OPP table, clocks
> and power domain, and connect it to the DPU and USB/DP QMP PHY.
> 
> Signed-off-by: Balaji Kalkonda <[email protected]>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 87 
> ++++++++++++++++++++++++++++++++-
>  1 file changed, 85 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi 
> b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index e48a179d0722..155c590c8eb6 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -3565,6 +3565,7 @@ usb_dp_qmpphy: phy@88e8000 {
>                       #clock-cells = <1>;
>                       #phy-cells = <1>;
>  
> +                     mode-switch;

Not mentioned in the commit message.

>                       orientation-switch;
>  
>                       status = "disabled";
> @@ -3851,6 +3854,86 @@ mdss_dsi0_phy: phy@9ac1000 {
>  
>                               status = "disabled";
>                       };
> +
> +                     mdss_dp0: displayport-controller@9ad2000 {
> +                             compatible = "qcom,kaanapali-dp";
> +                             reg = <0x0 0x09ad2000 0x0 0x10c>,
> +                                   <0x0 0x09ad2200 0x0 0xc8>,
> +                                   <0x0 0x09ad3000 0x0 0x78>,
> +                                   <0x0 0x09ad4000 0x0 0xa0>;
> +
> +                             interrupts-extended = <&mdss 12>;
> +
> +                             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                      <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> +                                      <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> +                                      <&dispcc 
> DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> +                                      <&dispcc 
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> +

Please define all pixel clocks that are used by the DP controller. Is it
not MST-capable?

> +                             clock-names = "core_iface",
> +                                           "core_aux",
> +                                           "ctrl_link",
> +                                           "ctrl_link_iface",
> +                                           "stream_pixel";
> +
> +                             assigned-clocks = <&dispcc 
> DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> +                                               <&dispcc 
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> +                             assigned-clock-parents =
> +                                     <&usb_dp_qmpphy 
> QMP_USB43DP_DP_LINK_CLK>,

Don't break the line here.

> +                                     <&usb_dp_qmpphy 
> QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> +                             operating-points-v2 = <&dp_opp_table>;
> +
> +                             power-domains = <&rpmhpd RPMHPD_MX>;

MMCX. If you need to cast a vote on MX domain too, add second entry to
the power domains and handle it in the driver.

> +
> +                             phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
> +                             phy-names = "dp";
> +
> +                             #sound-dai-cells = <0>;
> +
> +                             status = "disabled";
> +

-- 
With best wishes
Dmitry

Reply via email to