On 10/5/2026 9:06 AM, Dmitry Baryshkov wrote:
On Tue, Sep 15, 2026 at 05:27:50PM +0800, Yongxing Mou wrote:
The INT2 GDSC on Kaanapali (SM8850) powers a subset of the DPU
source pipes (VIG2/VIG3/DMA5). Add it as a second power domain of
the display-controller (DPU) node, alongside the existing MMCX
performance-state power domain.
The MDSS node's CORE_GDSC is unaffected, since it continues to power
the rest of the MDSS hardware on its own.
Signed-off-by: Yongxing Mou <[email protected]>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index ace19b8b12d7..b3e3cd1d311c 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -3619,7 +3619,9 @@ mdss_mdp: display-controller@9801000 {
operating-points-v2 = <&mdp_opp_table>;
- power-domains = <&rpmhpd RPMHPD_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
Should it continue to be RPMHPD_MMCX or should it become
DISP_CC_MDSS_CORE_GDSC?
It should remain RPMHPD_MMCX, as this power domain is used by the DPU
OPP table for performance-state voting.
DISP_CC_MDSS_CORE_GDSC remains attached to the parent MDSS device
because it supplies hardware shared across the MDSS subsystem. Since the
DPU is a child of MDSS, it inherits access to this power domain through
the parent-child runtime PM hierarchy.
Only INT2 is attached directly to the DPU, as it exclusively powers a
subset of the DPU source pipes.
+ <&dispcc
DISP_CC_MDSS_CORE_INT2_GDSC>;
+ power-domain-names = "mmcx", "int2";
ports {
#address-cells = <1>;
--
2.43.0
