On 10/12/2026 5:35 PM, Dmitry Baryshkov wrote:
On Thu, Oct 08, 2026 at 10:53:46PM +0530, Mahadevan P wrote:
Currently, the DPU driver bases LM reservation off of the maximum
supported width for the layer mixer and an arbitrary MAX_HDISPLAY_SPLIT.
However, these limits are not hardware limits meaning that a single LM
can support higher resolutions.
Switch to basing LM reservation off of PINGPONG and DSC encoder hardware
limits.
This revision also adds clock-based mixer selection and a source-pipe
width guard for mixers without source split.
Assisted-by: LLM
Signed-off-by: Mahadevan P <[email protected]>
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Changes in v4:
- Rebased on msm-next, resolving conflicts.
- Added clock-based mixer selection and reused the helper in mode
validation.
- Added a source-pipe width guard for mixers without source split.
- Extended the catalog cleanup to newer platforms.
What was the issue that caused display breakage on the CRD as reported
by Xilin Wu? How did you fix it?
The v3 change allowed this mode to use one LM because its width fits
within the PINGPONG limit, without accounting for LM throughput. For the
reported 3840×2160@120 timing, a single LM requires 1036.8 MHz before
margin, exceeding the reported 600 MHz MDP clock. v4 adds clock-based LM
selection, retaining two LMs for this mode and addressing the allocation
issue.
The separate clock-validation requirement remains: the dual-pipe rate is
1188 / 2 = 594 MHz, increasing to 623.7 MHz with the 5% inefficiency
margin specified by the HPG. Xilin’s working test bypassed that check.
At 600 MHz, there is only about 1% headroom above 594 MHz, so success in
that configuration does not guarantee reliable operation across other
workloads, where underruns may still occur. We therefore cannot remove
the hardware programming guide prescribed 5% margin based on this test
alone.
Thanks,
Mahadevan
- Link to v3:
https://lore.kernel.org/r/[email protected]
