Document the eDP transmitter PHY with NaNeng IP block found on the RK3568 SoC. The PHY is controlled through the eDP PHY GRF registers, so its node is modeled as a child of the eDP PHY GRF syscon. Also add the "rockchip,rk3568-edp-phy-grf" compatible and the "edp-phy" child node reference to the Rockchip GRF schema.
Signed-off-by: Damon Ding <[email protected]> --- .../bindings/phy/rockchip,rk3568-edp-phy.yaml | 59 +++++++++++++++++++ .../devicetree/bindings/soc/rockchip/grf.yaml | 15 +++++ 2 files changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml new file mode 100644 index 000000000000..afe7bc3d839e --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3568-edp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip eDP Transmitter PHY with NaNeng IP block + +maintainers: + - Damon Ding <[email protected]> + - Heiko Stuebner <[email protected]> + +description: + On the RK3568 SoC the eDP PHY is controlled through the eDP PHY GRF + registers, therefore the PHY node is expected to be a child of the + eDP PHY GRF syscon node. + +properties: + compatible: + const: rockchip,rk3568-edp-phy + + clocks: + maxItems: 1 + + clock-names: + const: refclk + + "#phy-cells": + const: 0 + +required: + - compatible + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + edp_phy_grf: syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdcb0000 0x0 0x100>; + clocks = <&cru PCLK_EDPPHY_GRF>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3568-edp-phy"; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>; + clock-names = "refclk"; + #phy-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 7bcb4e2f47ec..8d4ced0145b8 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -93,6 +93,7 @@ properties: - rockchip,rk3399-grf - rockchip,rk3399-pmugrf - rockchip,rk3562-pmu-grf + - rockchip,rk3568-edp-phy-grf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf - rockchip,rk3576-ioc-grf @@ -156,6 +157,19 @@ allOf: $ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml# unevaluatedProperties: false + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-edp-phy-grf + + then: + properties: + edp-phy: + type: object + $ref: /schemas/phy/rockchip,rk3568-edp-phy.yaml# + unevaluatedProperties: false + - if: properties: compatible: @@ -309,6 +323,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3568-edp-phy-grf - rockchip,rk3576-dcphy-grf - rockchip,rk3576-vo1-grf - rockchip,rk3588-vo-grf -- 2.34.1
