Kaanapali (SM8850) has an additional INT2 GDSC that powers a subset of DPU source pipes (VIG2/VIG3/DMA5). Without enabling it, those pipes remain inaccessible.
This series describes CORE and INT2 as the DPU power domains, updates the DT bindings accordingly, and explicitly attaches both domains in the DPU driver. DPU performance-state votes on CORE are propagated through the genpd hierarchy to MMCX. Signed-off-by: Yongxing Mou <[email protected]> --- Changes in v3: - Replaced MMCX with CORE as the DPU power domain, keeping INT2 as the second domain (Dmitry) - Used generic "core" and "int2" power-domain names (Dmitry) - Propagated DPU OPP votes from CORE to its parent MMCX domain - Updated the Kaanapali MDSS example and fixed issues reported by dt_binding_check - Link to v2: https://lore.kernel.org/r/[email protected] Changes in v2: - Moved INT2 GDSC from MDSS to DPU, as it only powers DPU-local source pipes (Dmitry) - Dropped Glymur — only Kaanapali actually needs INT2 GDSC - Used if/then in DT binding to restrict second power domain to Kaanapali compatible only (Dmitry, Krzysztof) - Dropped PD_FLAG_NO_DEV_LINK, let device link auto-attach handle INT2 as runtime-PM supplier (Dmitry) - Link to v1: https://lore.kernel.org/r/[email protected] --- Yongxing Mou (3): dt-bindings: display: msm: Add INT2 GDSC to Kaanapali DPU drm/msm/dpu: Attach CORE and INT2 power domains on Kaanapali arm64: dts: qcom: Add INT2 GDSC to Kaanapali DPU .../bindings/display/msm/dpu-common.yaml | 19 +++++++++++-- .../bindings/display/msm/qcom,kaanapali-mdss.yaml | 4 ++- .../bindings/display/msm/qcom,sm8650-dpu.yaml | 21 ++++++++++++++ arch/arm64/boot/dts/qcom/kaanapali.dtsi | 4 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 32 ++++++++++++++++++++++ 5 files changed, 76 insertions(+), 4 deletions(-) --- base-commit: 1fffefb00cc0b0da1f2ae24e3d33364530ea6515 change-id: 20260720-msm_gdsc2-cb9230027a2d Best regards, -- Yongxing Mou <[email protected]>
