Thank you for your contribution! Sashiko AI review found 2 potential issue(s) 
to consider:
- [High] dts: qcom: swapped regulators in usb_1_qmpphy
- [Medium] dts: qcom: sdm845-hdk: home_pin_a pinctrl incorrectly configures 
gpio6 instead of gpio5
--

commit b19f01b97eae7ab58c2051c6b112862e84428095
Author: Dmitry Baryshkov <[email protected]>

arm64: dts: qcom: add device tree for SDM845-HDK

Add device tree for the Qualcomm / Lantronix SDM845 HDK. It is the
development platform using the modem-less (SDA845) SoC, optional onboard
DSI panel and a rich set of connectors.

> diff --git a/arch/arm64/boot/dts/qcom/sdm845-hdk.dts 
> b/arch/arm64/boot/dts/qcom/sdm845-hdk.dts
> new file mode 100644
> index 0000000000000..450bbb9b9d19d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-hdk.dts
> @@ -0,0 +1,824 @@

[ ... ]

> +     gpio-keys {
> +             compatible = "gpio-keys";
> +             autorepeat;
> +
> +             pinctrl-names = "default";
> +             pinctrl-0 = <&home_pin_a>, <&vol_up_pin_a>;
> +
> +             key-home {
> +                     label = "Home";
> +                     linux,code = <KEY_HOMEPAGE>;
> +                     gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>;
> +             };

[ ... ]

> +&pm8998_gpios {
> +     home_pin_a: home-active-state {
> +             pins = "gpio6";

[Severity: Medium]
Is this pinctrl configuration targeting the wrong pin?

The key-home node maps the Home button to PMIC GPIO 5, but its assigned
pinctrl state home_pin_a here configures gpio6. This might cause the
physical Home button to float or fail to work properly.

> +             function = "normal";
> +             input-enable;
> +             bias-pull-up;
> +             qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> +     };

[ ... ]

> +&usb_1_qmpphy {
> +     vdda-phy-supply = <&vreg_l26a_1p2>;
> +     vdda-pll-supply = <&vreg_l1a_0p88>;

[Severity: High]
Are these regulator assignments inverted?

Across other QMP PHYs for SDM845 (like pcie0_phy and ufs_mem_phy), the 0.88V
regulator is mapped to the core PHY supply and the 1.2V regulator to the
PLL supply. Reversing these voltages applies 1.2V to the 0.88V domain and
0.88V to the 1.2V domain, which may lead to hardware damage or cause the
USB3 PHY to fail.

> +
> +     status = "okay";
> +};

-- 
Sashiko AI review ยท 
https://sashiko.dev/#/patchset/[email protected]?part=4

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