On Fri, Oct 16, 2026 at 06:40:50PM -0300, Helen Koike wrote:
> CTX_CS_INDIRECT_CTX_OFFSET default value is not retrieved from the GPU
> by inhibit+context save mechanism since it is not part of the Engine
> Context. Thus, at restore, 0x0 is programmed back to the GPU, which is
> an invalid value according to the PRM.
>
> This causes sporadic hangs on Alder Lake when executing test
> IntelAngleEnd2EndTestCases (error VK_DEVICE_LOST).
>
> Fix it by partially reverting commit c9dfd66cb91e ("drm/xe/lrc: Allow
> INDIRECT_CTX for more engine classes"). Re-add the programming of
> CTX_CS_INDIRECT_CTX_OFFSET for pre-Xe2 (in theory it should apply to all
> platforms, but we got an unexpected behaviour on Xe2 that still requires
> investigation).
>
> Fixes: c9dfd66cb91e ("drm/xe/lrc: Allow INDIRECT_CTX for more engine classes")
> Suggested-by: Tvrtko Ursulin <[email protected]>
> Signed-off-by: Helen Koike <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
>
> ---
>
> v3:
> - Commit message update:
> - s/programed/programmed
> - s/for ADL/for pre-Xe2
> - Add sentence saying it should apply to Xe2 too, but we got an
> unexpected behaviour and it requires more investigation.
> - Remove comment "Enable INDIRECT_CTX leaving..." since it is wrong.
>
> v2:
> - according to intel CI results, it seems that this default is not valid for
> LNL and BMG platforms, so limit the change only to ADL.
> - program the default only on ADL.
> - restore the comment, but add note with exception for ADL.
> - update the commit title/message with "for ADL".
> ---
> drivers/gpu/drm/xe/regs/xe_lrc_layout.h | 3 +++
> drivers/gpu/drm/xe/xe_lrc.c | 8 ++++----
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> index 4ab86fc369fd..e4c7c3549735 100644
> --- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> +++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> @@ -43,4 +43,7 @@
> #define INDIRECT_CTX_RING_START_UDW (0x08 + 1)
> #define INDIRECT_CTX_RING_CTL (0x0a + 1)
>
> +#define CTX_INDIRECT_CTX_OFFSET_MASK REG_GENMASK(15, 6)
> +#define CTX_INDIRECT_CTX_OFFSET_DEFAULT
> REG_FIELD_PREP(CTX_INDIRECT_CTX_OFFSET_MASK, 0xd)
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 35b4e8289b5f..18f247bc8865 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1449,15 +1449,15 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct
> xe_hw_engine *hwe)
> finish_bo(&state);
> kfree(state.buffer);
>
> - /*
> - * Enable INDIRECT_CTX leaving INDIRECT_CTX_OFFSET at its default: it
> - * varies per engine class, but the default is good enough
> - */
> xe_lrc_write_ctx_reg(lrc,
> CTX_CS_INDIRECT_CTX,
> (xe_bo_ggtt_addr(lrc->bo) + state.offset) |
> /* Size in CLs. */
> (state.written * sizeof(u32) / 64));
> + if (GRAPHICS_VER(lrc_to_xe(lrc)) < 20)
> + xe_lrc_write_ctx_reg(lrc,
> + CTX_CS_INDIRECT_CTX_OFFSET,
> + CTX_INDIRECT_CTX_OFFSET_DEFAULT);
>
> return 0;
> }
> --
> 2.54.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
