Thank you for your contribution! Sashiko AI review found 1 potential issue(s) 
to consider:
- [Low] dt-bindings: display: tegra: unvalidated dbi example and missing 
$nodename
--

commit 8ceaec80ccd97a96cf07da8add147a083a0f5944
Author: Svyatoslav Ryhel <[email protected]>

dt-bindings: display: tegra: Document 8-bit CPU parallel interface

This commit adds a devicetree binding schema for the 8-bit CPU parallel
MIPI DBI Type B interface on Tegra20 and Tegra30 display controllers, and
references it from the Tegra20 display controller binding.

> diff --git 
> a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml 
> b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml
> new file mode 100644
> index 0000000000000..ada7b35778933
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml
> @@ -0,0 +1,138 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra-dbi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nvidia Tegra DC based MIPI DBI Type B interface
> +
> +maintainers:
> +  - Svyatoslav Ryhel <[email protected]>
> +
> +description: The display controller in Tegra20/30 SoCs features an
> +  8-bit SPI interface that closely resembles the MIPI DBI Type B
> +  protocol and is referred to as '8-bit CPU'. Each display controller
> +  provides two such interfaces, which can be used to send MIPI DCS
> +  commands to initialize and control the panel while image data is
> +  transmitted via 16/18/24-line RGB.
> +
> +properties:
> +  dc-gpios:
> +    description: Data/command selection pin.
> +    maxItems: 1
> +
> +  rw-gpios:
> +    description: Read/write pin.
> +    maxItems: 1
> +
> +  cs-gpios:
> +    description: Chip select pin.
> +    maxItems: 1
> +
> +  data-gpios:
> +    description: Specifies a set of 8 gpio pins used to transfer data.
> +    minItems: 8
> +    maxItems: 8
> +
> +  nvidia,init-sequence:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description:
> +      Device specific set of values used in DC DISP_SPI_INIT_SEQ registers.
> +    minItems: 4
> +    maxItems: 4
> +
> +  panel:
> +    type: object
> +    description: Node of supported panel driven by the bridge.

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/gpio/gpio.h>
> +
> +    dbi {
> +        dc-gpios = <&gpio 110 GPIO_ACTIVE_HIGH>;
> +        rw-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
> +        cs-gpios = <&gpio 108 GPIO_ACTIVE_HIGH>;
> +
> +        data-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>, <&gpio 33 
> GPIO_ACTIVE_HIGH>,
> +                     <&gpio 34 GPIO_ACTIVE_HIGH>, <&gpio 35 
> GPIO_ACTIVE_HIGH>,
> +                     <&gpio 36 GPIO_ACTIVE_HIGH>, <&gpio 37 
> GPIO_ACTIVE_HIGH>,
> +                     <&gpio 38 GPIO_ACTIVE_HIGH>, <&gpio 39 
> GPIO_ACTIVE_HIGH>;
> +
> +        nvidia,init-sequence = <0x0000002c 0x0 0x0 0x00005000>;
> +
> +        panel {
> +            compatible = "hit,tx10d07vm0baa";
> +
> +            reset-gpios = <&gpio 175 GPIO_ACTIVE_LOW>;
> +
> +            avci-supply = <&vcc_2v8_lcd>;
> +            iovcc-supply = <&iovcc_1v8_lcd>;
> +
> +            backlight = <&backlight>;
> +
> +            port {
> +                panel_input: endpoint {
> +                    remote-endpoint = <&bridge_output>;
> +                };
> +            };
> +        };
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                reg = <0>;
> +
> +                bridge_input: endpoint {
> +                    remote-endpoint = <&dpi_output>;
> +                    bus-width = <24>;
> +                };
> +            };
> +
> +            port@1 {
> +                reg = <1>;
> +
> +                bridge_output: endpoint {
> +                    remote-endpoint = <&panel_input>;
> +                };
> +            };
> +        };
> +    };

[Severity: Low]
Because Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml
defines neither compatible, $nodename (for example, $nodename: const: dbi),
nor a select block, dt-mk-schema generates select: false for this schema. As
a result, the schema is only evaluated when referenced via $ref from the dbi
property of nvidia,tegra20-dc.yaml, and the standalone dbi node in examples
is never selected or validated by dt-validate against nvidia,tegra-dbi.yaml.

In addition, at this point in the series, the panel node in the example uses
compatible = "hit,tx10d07vm0baa" and avci-supply = <&vcc_2v8_lcd>, which are
not documented until commit 5002ce93d3d5 ("dt-bindings: display: panel:
Document Hitachi TX10D07VM0BAA and LG LH400WV3 panels"), causing make
dt_binding_check to fail during bisection.

Also, the panel property is only defined as type: object without referencing
/schemas/display/panel/panel-common.yaml# or specifying additionalProperties
or unevaluatedProperties, and the bridge_input label on the port@0 endpoint
is unused.

Should properties in nvidia,tegra-dbi.yaml include $nodename: const: dbi (or
place the example inside a nvidia,tegra20-dc node) and reference
panel-common.yaml# for panel, with the panel binding ordered before this
patch so make dt_binding_check validates the example cleanly?

-- 
Sashiko AI review ยท 
https://sashiko.dev/#/patchset/[email protected]?part=3

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