On 10/16/26 2:53 PM, Ishu Brar via B4 Relay wrote:
> From: Ishu Brar <[email protected]>
>
> Unlike the rest of the A650 family, the A620 does not get its PDC set up
> by AOP (the downstream devicetree has no pdc_in_aop for it). Without the
> sequence, the RSC never acks the second power-up ("Unable to power on
> the GPU RSC") and the device hangs.
>
> Program the sequence from the driver, taking the xo, mx and cx resource
> addresses from cmd-db instead of the hardcoded ones.
>
> Assisted-by: Claude
> Signed-off-by: Ishu Brar <[email protected]>
> ---
There's also this hunk in kgsl:
_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2,
xo_resource_addr);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0);
====
if (vrm_resource_addr && adreno_is_a620(adreno_dev)) {
_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 3,
0x10108);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 3,
vrm_resource_addr + 0x4);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 3,
0x0);
}
====
_regwrite(cfg, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
_regwrite(cfg, PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
_regwrite(cfg, PDC_GPU_TCS3_CONTROL, 0);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
if vrm.soc exists (presumably because a620 shipped on a number of socs?)
Konrad
