Three changes to how the A508, A509 and A512 power up and down, found running a phone shell on an SDM630 phone. The first resets the GPU on every resume: on SDM630, SDM660 and MSM8998 the GPU's GX power domain belongs to its SMMU, so a GPU resumed soon after suspending keeps its state, and its CP runs stale ringbuffer contents and hangs. The second holds a CPU latency request while the GPU is powered, as the downstream driver does: on SDM630 the GPU stops executing while the SoC is in system-level power collapse, so a submission overlapping such a state would stall and trip the hang detector. The third powers these GPUs down after downstream's 80 ms idle instead of the A530's 250 ms, so the request is released when downstream releases it.
The second patch adds code next to the first's, and the third sits on the second. Tested on a Motorola Moto X4 (SDM630, A508), whose board file is not in mainline yet, on sdm660-mainline's 7.2 kernel. The stall the second patch prevents was measured with an SDM630 system-level idle state that is not in mainline. --- Changes in v2: - Patch 1: take devfreq's busy-cycle baseline again after the reset, which clears the busy counter (Sashiko) - Link to v1: https://patch.msgid.link/[email protected] --- Fabricio Akio (3): drm/msm/a5xx: Reset the GPU when resuming it drm/msm/a5xx: Hold a CPU latency request while the GPU is powered drm/msm/a5xx: Use the downstream GPU idle timeout on A508, A509 and A512 drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 21 ++++++--------------- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ drivers/gpu/drm/msm/msm_gpu.h | 1 + drivers/gpu/drm/msm/msm_gpu_devfreq.c | 17 +++++++++++++++++ 6 files changed, 61 insertions(+), 15 deletions(-) --- base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64 change-id: 20261019-a5xx-gpu-pm-f58bc4ee2387 Best regards, -- Fabricio Akio <[email protected]>
