Quoting Andi Shyti (2026-10-28 13:57:39) > Hi Jia, > > On Fri, Oct 16, 2026 at 03:31:02AM +0000, Jia Yao wrote: > > Wa_22013059131 sets FORCE_1_SUB_MESSAGE_PER_FRAGMENT in LSC_CHICKEN_BIT_0 > > at engine init, but this is known to cause GPU hangs in certain workloads. > > Add I915_CONTEXT_PARAM_WA_22013059131 so userspace that handles the > > workaround itself (e.g. by limiting SLM size) can set it to 1 to let the > > kernel know bit 15 programming is not needed. The register is not > > context-saved by hardware, so the value is programmed on context switch > > via the indirect context batchbuffer, and the old unconditional write in > > intel_workarounds.c is removed. > > ... > > > Bspec: 54833 > > Link: https://github.com/intel/compute-runtime/pull/919 > > Cc: [email protected] > > Cc: Shuicheng Lin <[email protected]> > > Cc: Matt Roper <[email protected]> > > Cc: Joonas Lahtinen <[email protected]> > > Cc: Rodrigo Vivi <[email protected]> > > Cc: Maciej Plewka <[email protected]> > > Cc: Andi Shyti <[email protected]> > > Signed-off-by: Jia Yao <[email protected]> > > pushed to drm-intel-gt-next.
We're still lacking tests. I have reverted it for now. Regards, Joonas > > Thanks, > Andi
