Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] arm64: dts: qcom: sa8540p: unpreserved PCIe address maps for pcie2b/3b/4 --
commit 367f523cda7b8c336244029f70635c13b0b90574 Author: Xilin Wu <[email protected]> arm64: dts: qcom: sc8280xp: enable PCIe ECAM and 64-bit memory This commit enables PCIe ECAM and 64-bit memory windows for all five PCIe controllers in sc8280xp.dtsi, while preserving the 32-bit address map for pcie2a in sa8540p.dtsi to avoid regressions on SA8540P platforms. > diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi > b/arch/arm64/boot/dts/qcom/sa8540p.dtsi > index 23888029cc117..e5393a237497c 100644 > --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi > @@ -180,6 +180,15 @@ &gpu_smmu { > > &pcie2a { > compatible = "qcom,pcie-sa8540p"; > + reg = <0x0 0x01c20000 0x0 0x3000>, > + <0x0 0x3c000000 0x0 0xf1d>, > + <0x0 0x3c000f20 0x0 0xa8>, > + <0x0 0x3c001000 0x0 0x1000>, > + <0x0 0x3c100000 0x0 0x100000>, > + <0x0 0x01c23000 0x0 0x1000>; > + > + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, > + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; [Severity: High] Should the 32-bit reg and ranges properties also be preserved for pcie2b, pcie3b, and pcie4 in arch/arm64/boot/dts/qcom/sa8540p.dtsi? While pcie3a already defines its own reg and ranges overrides in sa8540p.dtsi, the remaining controllers in that file do not: arch/arm64/boot/dts/qcom/sa8540p.dtsi: &pcie2b { compatible = "qcom,pcie-sa8540p"; linux,pci-domain = <1>; interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; }; ... &pcie3b { compatible = "qcom,pcie-sa8540p"; linux,pci-domain = <3>; interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; }; &pcie4 { compatible = "qcom,pcie-sa8540p"; linux,pci-domain = <4>; interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; }; Boards such as arch/arm64/boot/dts/qcom/sa8295p-adp.dts include sa8540p.dtsi and enable pcie3b and pcie4: arch/arm64/boot/dts/qcom/sa8295p-adp.dts: &pcie3b { pinctrl-names = "default"; pinctrl-0 = <&pcie3b_default>; status = "okay"; }; ... &pcie4 { pinctrl-names = "default"; pinctrl-0 = <&pcie4_default>; status = "okay"; }; Without reg and ranges overrides in sa8540p.dtsi, pcie2b, pcie3b, and pcie4 inherit the new 64-bit ECAM config regions (at 0x4_c0000000, 0x4_40000000, and 0x4_00000000) and 64-bit MMIO windows from sc8280xp.dtsi. When qcom_pcie_probe() -> dw_pcie_host_init() -> pci_host_probe() runs on SA8540P/SA8295P platforms, won't accessing those SC8280XP 64-bit address ranges cause a regression due to the differing SA8540P memory map and firmware protection rules? -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=1
