Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] arm64: dts: qcom: sa8540p: missing reg and ranges on pcie2b, pcie3b, pcie4 --
commit 835660c7a888130654e80196f354e12277da4a3f Author: Xilin Wu <[email protected]> arm64: dts: qcom: sc8280xp: enable PCIe ECAM and 64-bit memory This commit updates the SC8280XP PCIe nodes to use 64-bit ECAM configuration spaces and adds 64-bit memory windows, while preserving the 32-bit address map on SA8540P for PCIe2a. > diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi > b/arch/arm64/boot/dts/qcom/sa8540p.dtsi > index 23888029cc117..e5393a237497c 100644 > --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi > @@ -180,6 +180,15 @@ &gpu_smmu { > > &pcie2a { > compatible = "qcom,pcie-sa8540p"; > + reg = <0x0 0x01c20000 0x0 0x3000>, > + <0x0 0x3c000000 0x0 0xf1d>, > + <0x0 0x3c000f20 0x0 0xa8>, > + <0x0 0x3c001000 0x0 0x1000>, > + <0x0 0x3c100000 0x0 0x100000>, > + <0x0 0x01c23000 0x0 0x1000>; > + > + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, > + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; [Severity: High] Should the legacy 32-bit reg and ranges properties also be preserved on &pcie2b, &pcie3b, and &pcie4 in arch/arm64/boot/dts/qcom/sa8540p.dtsi? This patch updates all five PCIe controllers in arch/arm64/boot/dts/qcom/sc8280xp.dtsi (pcie4, pcie3b, pcie3a, pcie2b, and pcie2a) to use the 64-bit ECAM config and MMIO address windows, but arch/arm64/boot/dts/qcom/sa8540p.dtsi only preserves the 32-bit windows for &pcie2a (and &pcie3a, which already overrides reg and ranges): arch/arm64/boot/dts/qcom/sa8540p.dtsi: &pcie2b { compatible = "qcom,pcie-sa8540p"; linux,pci-domain = <1>; interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; }; ... &pcie3b { compatible = "qcom,pcie-sa8540p"; linux,pci-domain = <3>; interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; }; &pcie4 { compatible = "qcom,pcie-sa8540p"; linux,pci-domain = <4>; interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; }; Meanwhile, arch/arm64/boot/dts/qcom/sa8295p-adp.dts includes sa8540p.dtsi and enables both &pcie3b and &pcie4 without overriding reg or ranges: arch/arm64/boot/dts/qcom/sa8295p-adp.dts: &pcie3b { pinctrl-names = "default"; pinctrl-0 = <&pcie3b_default>; status = "okay"; }; ... &pcie4 { pinctrl-names = "default"; pinctrl-0 = <&pcie4_default>; status = "okay"; }; As noted in commit b8bf63f8eb72 ("arm64: dts: qcom: sa8540p-ride: enable PCIe support"), accessing unconfigured PCIe address windows on SA8540P/SA8295P TrustZone firmware causes the board to crash into ramdump mode. When qcom_pcie_probe() -> dw_pcie_host_init() runs on SA8295P-ADP (or any SA8540P board enabling pcie2b, pcie3b, or pcie4), won't those controllers inherit the SC8280XP 64-bit address ranges (0x4_00000000..0x4_ffffffff) and trigger a crash at boot? -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=1
