Document 8-bit CPU parallel MIPI DBI Type B interface provided by Tegra20/30 SoCs display controller.
Reviewed-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Svyatoslav Ryhel <[email protected]> --- .../display/tegra/nvidia,tegra20-dbi.yaml | 113 ++++++++++++++++++ .../display/tegra/nvidia,tegra20-dc.yaml | 22 ++++ 2 files changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml new file mode 100644 index 0000000000000..cd568d19c363a --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dbi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nvidia Tegra Display Controller based MIPI DBI Type B interface + +maintainers: + - Svyatoslav Ryhel <[email protected]> + +description: The display controller in Tegra20/30 SoCs features an + 8-bit SPI interface that closely resembles the MIPI DBI Type B + protocol and is referred to as '8-bit CPU'. Each display controller + provides two such interfaces, which can be used to send MIPI DCS + commands to initialize and control the panel while image data is + transmitted via 16/18/24-line RGB. + +properties: + reg: + maximum: 1 + description: DBI interface used 0 - primary, 1 - secondary. + + panel: + type: object + description: Node of supported panel driven by the bridge. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Video port for RGB input. + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + bus-width: + enum: [ 16, 18, 24 ] + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for DBI output (panel or connector). + + required: + - port@0 + - port@1 + +required: + - reg + - panel + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dc@54200000 { + reg = <0x54200000 0x00040000>; + + #address-cells = <1>; + #size-cells = <0>; + + dbi@0 { + reg = <0>; + + panel { + compatible = "hit,tx10d07vm0baa"; + + reset-gpios = <&gpio 175 GPIO_ACTIVE_LOW>; + + avci-supply = <&vcc_2v8_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + bus-width = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml index 69be95afd5627..ffeb124905dbf 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -79,6 +79,16 @@ properties: rgb: type: object + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^dbi@[0-1]$": + $ref: /schemas/display/tegra/nvidia,tegra20-dbi.yaml# + allOf: - if: properties: @@ -155,6 +165,18 @@ allOf: - const: wind - const: wint + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra114-dc + - nvidia,tegra124-dc + - nvidia,tegra210-dc + then: + patternProperties: + "^dbi@[0-1]$": false + additionalProperties: false required: -- 2.53.0
