Hi, On Tue, 13 Oct 2026 at 23:51, Cristian Ciocaltea <[email protected]> wrote: > if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) { > - unsigned int bpc = vcstate->output_bpc ?: 8; > + /* > + * YUV422 always transmits two 12-bit components per clock > + * cycle, regardless of the color depth, which from a rate > + * perspective is equivalent to three 8-bit RGB components. > + * Force 8 bpc here so the bandwidth check reflects the actual > + * TMDS rate and avoids an unnecessary DCLK source switch. > + */ > + unsigned int bpc = vcstate->output_mode == > ROCKCHIP_OUT_MODE_YUV422 ? > + 8 : (vcstate->output_bpc ?: 8);
The nested ternary is pretty violent; please write it out explicitly. Either way, the equivalent clock adjustment for YUV420 is handled in the setup_intf_mux() handler, so would it be better for YUV422 to also live there, rather than mashed in with bpc here? Cheers, Daniel
