On Mon, 26 Oct 2026 16:40:25 +0000, Lucas Tanure wrote:
> HDMI 2.0 asks the source to set TMDS_Bit_Clock_Ratio in the sink while
> the TMDS clock is stopped and to start the clock at least 1 ms later.
> vc4 writes the bit, and enables the scrambler, at the end of the enable
> sequence, long after the PHY has started, and clears it before the PHY
> stops. A sink that samples the bit when the clock appears never locks
> a 4K60 signal from a Raspberry Pi 5, while laptops that follow the
> order work on the same sink.
>
> [...]
Applied to drm-misc-fixes, thanks!
[1/3] drm/vc4: hdmi: power down the BCM2712 PHY when the output is disabled
commit: a59a60e6e9e3a1d5177b28577d935d5ee37ace66
[2/3] drm/vc4: hdmi: always cancel the scrambling work synchronously
commit: 2e47848f0d076dec66df3bc403214073cd2214ac
[3/3] drm/vc4: hdmi: enable scrambling before the TMDS clock starts
commit: 81383bd290a18f06ccf9b0bfb29e1a3ef73d9357
Best regards,
- Maíra
