The always-on counter of a5xx is in the GPU power domain and restarts on
every runtime resume and on recovery.

Save the counter before the GPU powers down or is reset, and restore the
offset once it is back up, before it runs anything.

Signed-off-by: Dmitry Baryshkov <[email protected]>
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 16c7335c4b1f..fbb92cadf94f 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1025,6 +1025,8 @@ static void a5xx_recover(struct msm_gpu *gpu)
        if (hang_debug)
                a5xx_dump(gpu);
 
+       adreno_timestamp_save(gpu);
+
        gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1);
        gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD);
        gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0);
@@ -1374,6 +1376,7 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
                a5xx_set_hwcg(gpu, true);
                /* Turn on sp_input_clk at HM level */
                gpu_rmw(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0xff, 0);
+               adreno_timestamp_restore(gpu);
                return 0;
        }
 
@@ -1399,6 +1402,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
        if (ret)
                DRM_ERROR("%s: timeout waiting for SP GDSC enable\n",
                        gpu->name);
+       else
+               adreno_timestamp_restore(gpu);
 
        return ret;
 }
@@ -1415,6 +1420,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
            adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))
                mask = 0x7;
 
+       adreno_timestamp_save(gpu);
+
        /* Clear the VBIF pipe before shutting down */
        gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, mask);
        spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) &
@@ -1432,8 +1439,10 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
        }
 
        ret = msm_gpu_pm_suspend(gpu);
-       if (ret)
+       if (ret) {
+               adreno_timestamp_restore(gpu);
                return ret;
+       }
 
        if (a5xx_gpu->has_whereami)
                for (i = 0; i < gpu->nr_rings; i++)
@@ -1824,6 +1833,8 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device 
*dev)
                return ERR_PTR(ret);
        }
 
+       adreno_timestamp_init(gpu);
+
        /* Set the speedbin value that is passed to userspace */
        if (adreno_read_speedbin(&pdev->dev, &speedbin) || !speedbin)
                speedbin = 0xffff;

-- 
2.47.3

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