The per-SoC bonded config carries the controller FIFO error group as two magic numbers: 0x001f0200 in ERR_INT_MASK0 and 0x44440400 in FIFO_STATUS. They are documented - FIFO_STATUS bitfields carry public names in dsi.xml (the command DMA FIFO underflow at bit 10 and the DLN0..DLN3 HS FIFO overflows at bits 18/22/26/30, whose OR is exactly 0x44440400), while ERR_INT_MASK0 has no field definitions in dsi.xml, so its side is spelled out from the bit layout: GENMASK(20, 16) | BIT(9) = 0x001f0200. The grouping is not guessed: the vendor driver's mask_error_intr() masks exactly these bits as one FIFO error group.
Name both groups (DSI_ERR_INT_MASK0_FIFO_ERRORS, DSI_FIFO_STATUS_FIFO_ERRORS), switch the sm8750 table to them and drop the TODO(doc) note now that the provenance lives in the macro comments. No functional change: both macro groups expand to the previous literals. Signed-off-by: Qianhui Xu <[email protected]> --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index aa44d9fcba..05d9e1a191 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -199,15 +199,37 @@ static const struct regulator_bulk_data sm8650_dsi_regulators[] = { * Bonded command-path data. Values are copied verbatim from the vendor-derived * in-tree code; the SM8750 compatible check in dsi_host.c/dsi_manager.c still * gates every use until the master link moves into this table as well. - * TODO(doc): err_clear_bits/err_cleanup_bits touch bits that dsi.xml does not - * describe (see reports/b5-per-soc-cfg-design-20261027.md, RFC-SCOPE R1). */ + +/* + * FIFO error bits of ERR_INT_MASK0. dsi.xml does not describe the layout of + * this register, so the mask bits are spelled out: bits 20:16 mask the high + * speed FIFO overflow group (bits 16:19 are the DLN0..DLN3 overflows, bit 20 + * is part of the group but carries no public name) and bit 9 is the command + * DMA FIFO underflow. The grouping is not guessed: the vendor driver's + * mask_error_intr() masks exactly these bits as one FIFO error group. + */ +#define DSI_ERR_INT_MASK0_FIFO_OVERFLOW GENMASK(20, 16) +#define DSI_ERR_INT_MASK0_CMD_DMA_FIFO_UNDERFLOW BIT(9) +#define DSI_ERR_INT_MASK0_FIFO_ERRORS \ + (DSI_ERR_INT_MASK0_FIFO_OVERFLOW | DSI_ERR_INT_MASK0_CMD_DMA_FIFO_UNDERFLOW) + +/* + * Matching sticky FIFO_STATUS bits, write-1-to-clear. These carry public names + * in dsi.xml: CMD_DMA_FIFO_UNDERFLOW at bit 10 and the DLN0..DLN3 HS FIFO + * overflows at bits 18/22/26/30. + */ +#define DSI_FIFO_STATUS_FIFO_ERRORS \ + (DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW | \ + DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW | DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW | \ + DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW | DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW) + static const struct msm_dsi_bonded_cfg sm8750_dsi_bonded_cfg = { .master_link_id = DSI_0, .cmd_dma_ctrl = DSI_CMD_DMA_CTRL_BROADCAST_EN | DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER, - .err_clear_bits = 0x001f0200, - .err_cleanup_bits = 0x44440400, + .err_clear_bits = DSI_ERR_INT_MASK0_FIFO_ERRORS, + .err_cleanup_bits = DSI_FIFO_STATUS_FIFO_ERRORS, .poll_timeout_us = 5000, /* 500 polls, 10 us apart */ .needs_link_clk_bump = true, .needs_sw_reset = true, -- 2.53.0
