On 26-11-02 13:50:26, Qianhui Xu wrote: > The SM8750 display clock controller provides, beside the MDSS core > reset, a block reset for the MDSS core INT2 interrupt controller. On > devices whose bootloader hands over with the display block still active, > the kernel so far reset only the MDSS core and left the INT2 block in > the state left behind by the bootloader; command-mode panel > initialisation then fails with command DMA timeouts and the display > comes up as backlight only, without a DRM device. > > Describe both block resets so that the MDSS reset returns the MDSS > blocks to a known state before any display hardware is programmed. > > Signed-off-by: Qianhui Xu <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
