On Sat, Oct 31, 2026 at 01:23:39PM +0530, Ishu Brar wrote: > Add the binding for the SM7250 Mobile Display Subsystem. It has the > same clocks and children as the SM8250 one, so it is modeled on > qcom,sm8250-mdss.yaml. The example uses the SM8250 clock and
No DisplayPort? > interconnect headers, as the SM7250 ones are not upstream yet. > > Signed-off-by: Ishu Brar <[email protected]> > --- > .../bindings/display/msm/qcom,sm7250-mdss.yaml | 351 > +++++++++++++++++++++ > 1 file changed, 351 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/display/msm/qcom,sm7250-mdss.yaml > b/Documentation/devicetree/bindings/display/msm/qcom,sm7250-mdss.yaml > new file mode 100644 > index 000000000000..aada943e0cf3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7250-mdss.yaml > @@ -0,0 +1,351 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm7250-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM7250 Display MDSS > + > +maintainers: > + - Ishu Brar <[email protected]> > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that > encapsulates s/Device tree bindings for MSM Mobile/SM7250 MSM Mobile/ > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device > tree > + bindings of MDSS are mentioned for SM7250 target. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm7250-mdss > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display hf axi clock > + - description: Display sf axi clock > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: nrt_bus > + - const: core > + > + iommus: > + maxItems: 1 > + > + interconnects: > + items: > + - description: Interconnect path from mdp0 port to the data bus > + - description: Interconnect path from mdp1 port to the data bus > + - description: Interconnect path from CPU to the reg bus > + > + interconnect-names: > + items: > + - const: mdp0-mem > + - const: mdp1-mem > + - const: cpu-cfg > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + additionalProperties: true > + Drop blank line > + properties: > + compatible: > + const: qcom,sm7250-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + additionalProperties: true > + Drop blank line > + properties: > + compatible: > + items: > + - const: qcom,sm7250-dsi-ctrl > + - const: qcom,mdss-dsi-ctrl > + > + "^phy@[0-9a-f]+$": > + type: object > + additionalProperties: true > + Drop blank line > + properties: > + compatible: > + const: qcom,dsi-phy-7nm Best regards, Krzysztof
