The UBWC entry for DRM_FORMAT_P010 is set up for P030 (TP10), three
10-bit samples in each 32-bit word, the layout the video decoders
produce for QC10C. It doesn't match P010: compressed P010, as the GPU
writes it, keeps 16-bit samples and is scanned out as garbage.
Use DRM_FORMAT_P030 for that entry, compressed only, as the SSPP can't
fetch linear P030, and give P010 its own UBWC entry with 16-bit samples.
This changes what compressed P010 means. Nothing is known to depend on
the old meaning: Mesa and minigbm never allocate it, the vendor stack
uses its own modifier bits, and the only user found is a draft
GStreamer merge request.
Fixes: f07c9946cc1a ("drm/msm/dpu: Add support for P010 format")
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +++-
drivers/gpu/drm/msm/disp/mdp_format.c | 13 +++++++++----
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 107150a8553f..f755c0d57abe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -173,6 +173,7 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_BGRX4444,
DRM_FORMAT_P010,
+ DRM_FORMAT_P030,
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
DRM_FORMAT_NV16,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 1a471cdf767b..09146023d13e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -68,6 +68,7 @@ static const uint32_t qcom_compressed_supported_formats[] = {
DRM_FORMAT_NV12,
DRM_FORMAT_P010,
+ DRM_FORMAT_P030,
};
/*
@@ -1779,8 +1780,9 @@ static bool dpu_plane_format_mod_supported(struct
drm_plane *plane,
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
bool has_no_ubwc = (dpu_kms->mdss->ubwc_enc_version == 0);
+ /* the SSPP can only fetch P030 compressed */
if (modifier == DRM_FORMAT_MOD_LINEAR)
- return true;
+ return format != DRM_FORMAT_P030;
if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED && !has_no_ubwc)
return dpu_find_format(format,
qcom_compressed_supported_formats,
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c
b/drivers/gpu/drm/msm/disp/mdp_format.c
index 33da569eae5e..2712a73e5783 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -298,8 +298,7 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = MDP_FETCH_UBWC, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- MSM_FORMAT_FLAG_YUV | \
+ .flags = MSM_FORMAT_FLAG_YUV | \
MSM_FORMAT_FLAG_COMPRESSED | flg, \
.num_planes = 4, \
.tile_height = th \
@@ -606,13 +605,19 @@ static const struct msm_format mdp_formats_ubwc[] = {
PSEUDO_YUV_FMT_TILED(NV12,
BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, 0,
+ CHROMA_420, MSM_FORMAT_FLAG_UNPACK_TIGHT,
MDP_TILE_HEIGHT_NV12),
+ PSEUDO_YUV_FMT_TILED(P030,
+ BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_UNPACK_TIGHT | MSM_FORMAT_FLAG_DX,
+ MDP_TILE_HEIGHT_UBWC),
+
PSEUDO_YUV_FMT_TILED(P010,
BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_DX,
+ CHROMA_420, MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB |
MSM_FORMAT_FLAG_DX,
MDP_TILE_HEIGHT_UBWC),
};
--
2.47.3
