On Wednesday 24 April 2002 06:15 am, you wrote: Hi, there!
> For enabling DMA on Mach64 I'll need to allocate two extra DMA buffers: a > primary DMA buffer and a decription table buffer. All you need for now is a descriptor table. The buffers that you have already allocated via the DRM's framework should be allocated page aligned and you'll have the bus address in hand. The only reason you'd need a "primary" buffer is if you had an engine that wasn't at all secure (The RagePRO's pretty much secure, it won't let you set up DMA sessions, etc. and you can undo anything that might cause confusion in the engine at the end of the pass (Use the Utah-GLX code for the closeout of a DMA pass for a hint there...).) and you're "securing" the vertex path. For now, I'd be seeing what you can do to just get it going. All you need is a descriptor table at that point. Use the memory pool api to allocate that one just like in the BUS-Master test. At that point, we'll have a DMA system (Though it ties up the framework for any given pass- the code I'm completing happens to have a full-blown queue, etc that is governed by the CTRC interrupt.). It may not be quite what I have in hand, but as Gareth has said before, get it working- I'm just waay to busy to have completed what I had in mind up until recently. -- Frank Earl _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
