On Thu, 2002-07-18 at 16:40, Keith Whitwell wrote:
> Henry Worth wrote:
> >
> > Michel,
> >
> > How do these changes for r128 COMMIT_RING look? With these I can run
> > concurrent xine and glx programs in pci and agp mode with XV dma
> > disabled.
> >
> > With XV dma enabled, in both pci and agp mode, I can run xine for some
> > time without any hangs. But startup a glx program and X will hang until I
> > kill the glx program, and then X and xine will recover. I guess sync is the
> > next issue, I have a follow-on question on that below.
> >
> > The patch also includes a change to RING_SPACE_TEST..., based on
> > the radeon version, adding a register read fallback for determining ring
> > space.
>
> I have no idea why there is a need for the RING_SPACE_TEST macro. It's
> disabled in the r200 branch.
Besides, I've never hit the added code there.
> > The current drm r128 does not have any WAIT_UNTIL_*_IDLE macros.
> > I assume I'm going to need at least a general idle wait to address sync
> > issues. The only WAIT_UNTIL mask bit defined in r128_drv.h is for page
> > flip, are there any other bits available for wait functions?
>
> What does the r128 currently do to synchronize access to the framebuffer?
XAA handles that, and both drivers provide WaitForIdle() as the Sync
function.
> It may be that 2d & 3d are synchronized by the hardware automatically,
I doubt that, e.g. the texture blit ioctl also flushes the pixel cache.
Maybe there's more to do with the PC_{,N}GUI_* registers?
> but you'll always need to do something before accessing the framebuffer
> directly.
I don't see where direct framebuffer access is involved when using DMA
transfers for Xv.
--
Earthling Michel Dänzer (MrCooper)/ Debian GNU/Linux (powerpc) developer
XFree86 and DRI project member / CS student, Free Software enthusiast
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