Tom Hosiawa wrote:
> What exactly is drm_radeon_depth_clear_t storing; is it registers on the card having
>something to do with the way depth buffers get used???
If you look at where it's used, you get a clue that these are register values:
OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
depth_clear->rb3d_zstencilcntl );
However, some explanation might help:
Radeons can (with the docs we have) only clear the depth buffer via the 3d
engine -- by drawing a quad with z-testing disabled, a planemask so no colors
get drawn, and various other state set the right way.
The register values stored in drm_r_d_c_t are the values needed to set the
card into a state to draw the quad.
Keith
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