Around 1 o'clock on Oct 23, Alan Cox wrote: > Uncached writes on PC hardware are almost always a complete loss. You > want the writeback caching so you are writing to the PCI bridge or sdram > in the largest chunk sizes possible.
The problem with cached writes is that each cacheline will be brought into cache when the first write is issued. If the memory is across the PCI (or AGP) bus, that takes a long time. Combine that effect with cache pollution and the overall performance is almost certainly slower than write combining mode, which is no speed daemon either. The answer is different when writing to memory; cacheline fills across the memory bus are a lot faster than across AGP. If the data really is small enough to fit in the L2 cache, then things will improve even further. This argues for very small buffers; syscall context switches may well be cheaper than a large number of trips to memory, especially on more recent hardware. Keith Packard XFree86 Core Team HP Cambridge Research Lab ------------------------------------------------------- This sf.net emial is sponsored by: Influence the future of Java(TM) technology. Join the Java Community Process(SM) (JCP(SM)) program now. http://ad.doubleclick.net/clk;4699841;7576301;v?http://www.sun.com/javavote _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
