On Thu, 17 Oct 2002, Marc Aurele La France wrote: >> The problem WAS that this re-enabling did not always take place before >> Marc's changes, which is why we added the explicit call to do this. I've >> checked the code in current XFree86 CVS, but would very much like to know >> (just for interest's sake) WHERE exactly the PCI enable (or whatnot) is >> called from that re-enables bus mastering after a VT switch. > >The question on my, and David's, mind is whether or not bus mastering was >enabled on server entry.
I can't say for every reported case, but I can say that on the cases I examined personally, that the video hardware had Bus Mastering enabled prior to the X server being started (lspci -vvv), as well as while the X server was running. Switching to a VT and doing lspci -vvv then showed bus mastering disabled. I witnessed this on 3 different systems personally, and via testing feedback from various users got similar responses back. Not sure if all systems were this way, but some were at least. For the current CVS code, I don't know if the problem is present or not. I've disabled Charl's patch for now in order to have the stock code well tested. Our kernel hasn't been updated with the latest DRM source however, so testing hasn't begun yet. Sometime in the next couple weeks I'll likely have our kernel DRM updated, and bang on the Radeon a bit. If the problems recur, I'll try out Charl's patch again, and possibly do a debug session with Charl and MrCooper again if they're game. Has anyone else already tested it for hanging? TTYL -- Mike A. Harris ------------------------------------------------------- This sf.net email is sponsored by: Access Your PC Securely with GoToMyPC. Try Free Now https://www.gotomypc.com/s/OSND/DD _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
