On Sat, 2002-12-14 at 03:41, Ian Romanick wrote: > On Fri, Dec 13, 2002 at 01:15:01PM -0800, Sottek, Matthew J wrote: > > > > The i810's vblank interrupt does not go to the CPU's interrupt > > controller IIRC. Therefore you have to poll for vblank by reading > > the current scanline. > > I fully expect that there's something that I'm missing, but shouldn't > setting bit 7 of IER (0x20a0) enable the vblank interrupt? I get this from > page 351 (363 of the pdf) of 'Intel 810 Chipset Family Programmer's > Reference Manual.' The i815 PRM says the same thing. It's section 16.2.2 > in both. > Yes, setting bit 7 of IER and clearing bit 7 of IMR will enable the primary display event interrupt. Setting bit 24 of DPLYSTAS will enable the specific vsync event. Then in the IRQ handler, just check if bit 9 is set which indicates the occurence of the vsync event. Before exiting from the handler, write a 1 to bit 7 of the IIR (and bit 9 of DPLYSTAS if a vsync did occur) to clear the event (lest you freeze the box).
I think what Matt was talking about is bits 4 and 5 of CR11. This doesn't go to the controller, so is pretty much useless. Tony ------------------------------------------------------- This sf.net email is sponsored by: With Great Power, Comes Great Responsibility Learn to use your power at OSDN's High Performance Computing Channel http://hpc.devchannel.org/ _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
