yuvrect.c seems to work texrect.c still doesnt work
any hints?
greetings, Andreas
Only in mod_trunk: build
Only in trunk_orig: cvs-logdatei
Only in trunk_orig: update_cvs
diff -ru trunk_orig/xc/xc/extras/Mesa/src/enums.c mod_trunk/xc/xc/extras/Mesa/src/enums.c
--- trunk_orig/xc/xc/extras/Mesa/src/enums.c Fri Apr 4 19:30:23 2003
+++ mod_trunk/xc/xc/extras/Mesa/src/enums.c Sat Jun 7 17:51:01 2003
@@ -885,6 +885,12 @@
/* GL_3DFX_texture_compression_FXT1 */
{ "GL_COMPRESSED_RGB_FXT1_3DFX", 0x86B0 },
{ "GL_COMPRESSED_RGBA_FXT1_3DFX", 0x86B1 },
+
+ /* GL_NV_texture_rectangle */
+ { "TEXTURE_RECTANGLE_NV", 0x84F5 },
+ { "TEXTURE_BINDING_RECTANGLE_NV", 0x84F6 },
+ { "PROXY_TEXTURE_RECTANGLE_NV", 0x84F7 },
+ { "MAX_RECTANGLE_TEXTURE_SIZE_NV", 0x84F8 },
};
#define Elements(x) sizeof(x)/sizeof(*x)
diff -ru trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c
--- trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c Mon Jun 2 22:41:52 2003
+++ mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c Sat Jun 7 17:51:01 2003
@@ -387,6 +387,8 @@
_math_matrix_set_identity( &rmesa->tmpmat );
driInitExtensions( ctx, card_extensions, GL_TRUE );
+ if( rmesa->dri.drmMinor >= 9 || getenv( "RADEON_RECTANGLE_FORCE_ENABLE")) /* FIXME! a.s. */
+ _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
radeonInitDriverFuncs( ctx );
radeonInitIoctlFuncs( ctx );
radeonInitStateFuncs( ctx );
diff -ru trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
--- trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h Sat May 17 08:24:40 2003
+++ mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h Sat Jun 7 17:51:01 2003
@@ -259,6 +259,11 @@
#define TEX_PP_BORDER_COLOR 8
#define TEX_STATE_SIZE 9
+#define TXR_CMD_0 0 /* rectangle textures */
+#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
+#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
+#define TXR_STATE_SIZE 3
+
#define ZBS_CMD_0 0
#define ZBS_SE_ZBIAS_FACTOR 1
#define ZBS_SE_ZBIAS_CONSTANT 2
@@ -422,6 +427,7 @@
struct radeon_state_atom grd; /* guard band clipping */
struct radeon_state_atom fog;
struct radeon_state_atom glt;
+ struct radeon_state_atom txr[2]; /* for NPOT */
};
struct radeon_state {
diff -ru trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
--- trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c Wed May 21 21:07:51 2003
+++ mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c Sat Jun 7 17:51:01 2003
@@ -389,6 +389,72 @@
#endif
}
+/* using already shifted color_fmt! */
+void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is required? */
+ GLuint color_fmt,
+ GLuint src_pitch,
+ GLuint src_offset,
+ GLuint dst_pitch,
+ GLuint dst_offset,
+ GLint srcx, GLint srcy,
+ GLint dstx, GLint dsty,
+ GLuint w, GLuint h )
+{
+ drmRadeonCmdHeader *cmd;
+
+ if (RADEON_DEBUG & DEBUG_IOCTL)
+ fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
+ __FUNCTION__,
+ src_pitch, src_offset, srcx, srcy,
+ dst_pitch, dst_offset, dstx, dsty,
+ w, h);
+
+ assert( (src_pitch & 63) == 0 );
+ assert( (dst_pitch & 63) == 0 );
+ assert( (src_offset & 1023) == 0 );
+ assert( (dst_offset & 1023) == 0 );
+ assert( w < (1<<16) );
+ assert( h < (1<<16) );
+
+ cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
+ __FUNCTION__ );
+
+
+ cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
+ cmd[1].i = RADEON_CP_PACKET3_CNTL_BITBLT_MULTI | (5 << 16); /* FIXME: is this the right package? */
+ cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
+ RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+ RADEON_GMC_BRUSH_NONE |
+ color_fmt |
+ RADEON_GMC_SRC_DATATYPE_COLOR |
+ RADEON_ROP3_S |
+ RADEON_DP_SRC_SOURCE_MEMORY |
+ RADEON_GMC_CLR_CMP_CNTL_DIS |
+ RADEON_GMC_WR_MSK_DIS );
+
+ cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10);
+ cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10);
+ cmd[5].i = (srcx << 16) | srcy;
+ cmd[6].i = (dstx << 16) | dsty; /* dst */
+ cmd[7].i = (w << 16) | h;
+}
+
+
+void radeonEmitWait( radeonContextPtr rmesa, GLuint flags )
+{
+ if (rmesa->dri.drmMinor >= 6) {
+ drmRadeonCmdHeader *cmd;
+
+ assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
+
+ cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
+ __FUNCTION__ );
+ cmd[0].i = 0;
+ cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
+ cmd[0].wait.flags = flags;
+ }
+}
+
static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
const char * caller )
diff -ru trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.h mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.h
--- trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.h Fri May 2 13:01:53 2003
+++ mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.h Sat Jun 7 17:51:01 2003
@@ -65,7 +65,17 @@
GLuint n,
GLuint offset );
+extern void radeonEmitBlit( radeonContextPtr rmesa,
+ GLuint color_fmt,
+ GLuint src_pitch,
+ GLuint src_offset,
+ GLuint dst_pitch,
+ GLuint dst_offset,
+ GLint srcx, GLint srcy,
+ GLint dstx, GLint dsty,
+ GLuint w, GLuint h );
+extern void radeonEmitWait( radeonContextPtr rmesa, GLuint flags );
extern void radeonFlushCmdBuf( radeonContextPtr rmesa, const char * );
extern void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa );
diff -ru trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c
--- trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c Fri May 2 13:01:54 2003
+++ mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c Sat Jun 7 17:51:01 2003
@@ -134,6 +134,9 @@
TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
+CHECK( txr0, ctx->Texture.Unit[0]._ReallyEnabled )
+CHECK( txr1, ctx->Texture.Unit[1]._ReallyEnabled )
+
/* Initialize the context's hardware state.
@@ -246,6 +249,8 @@
ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
+ ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
+ ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
/* Fill in the packet headers:
@@ -268,6 +273,8 @@
rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
rmesa->hw.mtl.cmd[MTL_CMD_0] =
cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
+ rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0);
+ rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1);
rmesa->hw.grd.cmd[GRD_CMD_0] =
cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
rmesa->hw.fog.cmd[FOG_CMD_0] =
diff -ru trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c
--- trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c Fri May 2 13:01:55 2003
+++ mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c Sat Jun 7 19:31:00 2003
@@ -43,6 +43,7 @@
#include "simple_list.h"
#include "radeon_context.h"
+#include "radeon_ioctl.h"
#include "radeon_tex.h"
@@ -76,6 +77,96 @@
* Texture image conversions
*/
+
+static void radeonUploadRectSubImage( radeonContextPtr rmesa,
+ radeonTexObjPtr t,
+ struct gl_texture_image *texImage,
+ GLint x, GLint y,
+ GLint width, GLint height )
+{
+ const struct gl_texture_format *texFormat = texImage->TexFormat;
+ int blit_format, dstPitch, done;
+
+ switch ( texFormat->TexelBytes ) {
+ case 1:
+ blit_format = RADEON_GMC_DST_8BPP_CI;
+ break;
+ case 2:
+ blit_format = RADEON_GMC_DST_16BPP;
+ break;
+ case 4:
+ blit_format = RADEON_GMC_DST_32BPP;
+ break;
+ default:
+ fprintf( stderr, "radeonUploadRectSubImage: unknown blit_format (texelbytes=%d)\n",
+ texFormat->TexelBytes);
+ return;
+ }
+
+ t->image[0][0].data = texImage->Data;
+
+ /* Currently don't need to cope with small pitches.
+ */
+ width = texImage->Width;
+ height = texImage->Height;
+ dstPitch = t->pp_txpitch + 32;
+
+ { /* FIXME: prefer AGP-texturing if possible */
+ /* Data not in agp memory, or bad pitch.
+ */
+ for (done = 0; done < height ; ) {
+ struct radeon_dma_region region;
+ int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch );
+ int src_pitch;
+ char *tex;
+
+ src_pitch = texImage->RowStride * texFormat->TexelBytes;
+
+ tex = (char *)texImage->Data + done * src_pitch;
+
+ memset(®ion, 0, sizeof(region));
+ radeonAllocDmaRegion( rmesa, ®ion, lines * dstPitch, 64 );
+
+ /* Copy texdata to dma:
+ */
+ if (0)
+ fprintf(stderr, "%s: src_pitch %d dst_pitch %d\n",
+ __FUNCTION__, src_pitch, dstPitch);
+
+ if (src_pitch == dstPitch) {
+ memcpy( region.address, tex, lines * src_pitch );
+ }
+ else {
+ char *buf = region.address;
+ int i;
+ for (i = 0 ; i < lines ; i++) {
+ memcpy( buf, tex, src_pitch );
+ buf += dstPitch;
+ tex += src_pitch;
+ }
+ }
+
+ radeonEmitWait( rmesa, RADEON_WAIT_3D );
+
+ /* Blit to framebuffer
+ */
+ radeonEmitBlit( rmesa,
+ blit_format,
+ dstPitch, GET_START( ®ion ),
+ dstPitch, t->bufAddr,
+ 0, 0,
+ 0, done,
+ width, lines );
+
+ radeonEmitWait( rmesa, RADEON_WAIT_2D );
+
+ radeonReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ );
+ done += lines;
+ }
+ }
+}
+
+
/**
* Upload the texture image associated with texture \a t at the specified
* level at the address relative to \a start.
@@ -135,6 +226,16 @@
if ( !texImage->Data ) {
if ( RADEON_DEBUG & DEBUG_TEXTURE )
fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ );
+ return;
+ }
+
+
+ if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
+ assert(level == 0);
+ assert(hwlevel == 0);
+ if ( RADEON_DEBUG & DEBUG_TEXTURE )
+ fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__);
+ radeonUploadRectSubImage( rmesa, t, texImage, x, y, width, height );
return;
}
diff -ru trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c
--- trunk_orig/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c Mon Jun 2 22:41:53 2003
+++ mod_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c Sat Jun 7 19:32:00 2003
@@ -147,6 +147,11 @@
log2Height = tObj->Image[firstLevel]->HeightLog2;
log2Depth = 0;
break;
+ case GL_TEXTURE_RECTANGLE_NV:
+ firstLevel = lastLevel = 0;
+ log2Width = log2Height = 1; /* ? */
+ log2Depth = 0;
+ break;
default:
return;
}
@@ -177,6 +182,10 @@
if (texImage->IsCompressed) {
size = texImage->CompressedSize;
}
+ else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
+ size = ((texImage->Width * texImage->TexFormat->TexelBytes + 63)
+ & ~63) * texImage->Height;
+ }
else {
int w = texImage->Width * texImage->TexFormat->TexelBytes;
if (w < 32)
@@ -1262,9 +1271,16 @@
cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset;
cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
- texobj->dirty_state &= ~(1<<unit);
-
RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.tex[unit] );
+
+ if (texobj->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
+ GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
+ txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
+ txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
+ RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.tex[unit] );
+ }
+
+ texobj->dirty_state &= ~(1<<unit);
}
@@ -1461,6 +1477,31 @@
return GL_TRUE;
}
+static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
+{
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
+ struct gl_texture_object *tObj = texUnit->_Current;
+ radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
+
+ if (!(t->pp_txformat & RADEON_TXFORMAT_NON_POWER2)) {
+ t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
+ t->base.dirty_images[0] = ~0;
+ }
+
+ ASSERT(tObj->Target == GL_TEXTURE_RECTANGLE_NV);
+
+ if ( t->base.dirty_images[0] ) {
+ RADEON_FIREVERTICES( rmesa );
+ radeonSetTexImages( rmesa, tObj );
+ radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
+ if ( !t->base.memBlock /* && !rmesa->prefer_agp_client_texturing FIXME */ )
+ return GL_FALSE;
+ }
+
+ return GL_TRUE;
+}
+
static GLboolean update_tex_common( GLcontext *ctx, int unit )
{
@@ -1542,7 +1583,11 @@
{
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- if ( texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT) ) {
+ if ( texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT) ) {
+ return (enable_tex_rect( ctx, unit ) &&
+ update_tex_common( ctx, unit ));
+ }
+ else if ( texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT) ) {
return (enable_tex_2d( ctx, unit ) &&
update_tex_common( ctx, unit ));
}
diff -ru trunk_orig/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h mod_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h
--- trunk_orig/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h Mon Nov 25 21:20:38 2002
+++ mod_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h Sat Jun 7 17:51:01 2003
@@ -354,7 +354,10 @@
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
-#define RADEON_MAX_STATE_PACKETS 73
+#define RADEON_EMIT_PP_TEX_SIZE_0 73
+#define RADEON_EMIT_PP_TEX_SIZE_1 74
+#define RADEON_EMIT_PP_TEX_SIZE_2 75
+#define RADEON_MAX_STATE_PACKETS 76
/* Commands understood by cmd_buffer ioctl. More can be added but
diff -ru trunk_orig/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h mod_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
--- trunk_orig/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h Sat May 17 08:25:39 2003
+++ mod_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h Sat Jun 7 17:51:01 2003
@@ -1270,6 +1270,10 @@
# define RADEON_SIGNED_RGB_SHIFT 30
# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
# define RADEON_SIGNED_ALPHA_SHIFT 31
+#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
+#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
+#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
+/* note: bits 13-5: 32 byte aligned stride of texture map */
#define RADEON_PP_TXCBLEND_0 0x1c60
#define RADEON_PP_TXCBLEND_1 0x1c78
diff -ru trunk_orig/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h mod_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h
--- trunk_orig/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h Wed May 21 19:15:14 2003
+++ mod_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h Sat Jun 7 17:51:01 2003
@@ -141,7 +141,10 @@
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
-#define RADEON_MAX_STATE_PACKETS 73
+#define RADEON_EMIT_PP_TEX_SIZE_0 73
+#define RADEON_EMIT_PP_TEX_SIZE_1 74
+#define RADEON_EMIT_PP_TEX_SIZE_2 75
+#define RADEON_MAX_STATE_PACKETS 76
/* Commands understood by cmd_buffer ioctl. More can be added but
diff -ru trunk_orig/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h mod_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h
--- trunk_orig/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h Wed May 21 19:15:14 2003
+++ mod_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h Sat Jun 7 17:51:01 2003
@@ -669,6 +669,10 @@
#define R200_RE_POINTSIZE 0x2648
#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
+#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
+#define RADEON_PP_TEX_SIZE_1 0x1d0c
+#define RADEON_PP_TEX_SIZE_2 0x1d14
+
#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
diff -ru trunk_orig/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c mod_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c
--- trunk_orig/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c Mon Apr 28 23:08:56 2003
+++ mod_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c Sat Jun 7 17:51:01 2003
@@ -292,6 +292,9 @@
{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
+ { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
+ { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
+ { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
};
