On Sat, 2003-05-31 at 09:50, Paul Mackerras wrote: > I have been doing more hacking on the kernel DRM for rage 128 on my G4 > powerbook. This machine has a "UniNorth" v1.0 host bridge which can > (allegedly) do 2x AGP. I have got DRI with AGP to work but it is a > bit of a saga. The main problem is with the chip writing back the > ring read pointer. With the DRM code in CVS, every call to > r128_do_cce_idle() times out because it isn't seeing the read pointer > updated. > > I started with a patch by Ben Herrenschmidt to the r128 DRM which adds > a powermac-specific hack to reserve the last page of physical memory > and use that for the ring read pointer, rather than the piece of AGP > memory which is normally used for it. We then write the physical > address of that bit of memory into the R128_PM4_BUFFER_DL_RPTR_ADDR > register. > > I also split up ADVANCE_RING into separate ADVANCE_RING and > COMMIT_RING macros like the radeon DRM does, at Michel Daenzer's > suggestion. > > With that, DRI with AGP runs well on my powerbook at 1x. At 2x it > runs for a little while and then locks up the video chip, usually with > bizaare technicolor patterns. > > Ben's hack is a bit ugly, though, so I tried various things to see if > I could get the chip to write back anything to AGP memory. Nothing > worked.
I assume you have tried all variants for R128_PM4_BUFFER_DL_RPTR I proposed, e.g. adding R128_AGP_OFFSET? > So I tried another approach, which is to just read the > R128_PM4_BUFFER_DL_RPTR register when we need to know what the ring > head pointer is. That seems to work fine, with no slowdown in > performance that I could measure (with glxgears and tuxracer). I have > seen GL apps freeze up on a couple of occasions though. Possibly due to the bus traffic caused by reading the register keeping the chip from completing what it's doing? > Also, is there some simple test I could do to work out whether AGP > writes work at all? Maybe something like what the radeon driver uses to set dev_priv->writeback_works ? > Finally, if someone can explain how addresses that are programmed into > the card are mapped back to main memory, that would be very useful. > In particular, how does the card decide whether an address (for > instance in the R128_PM4_BUFFER_DL_RPTR_ADDR register) is a physical > address to be used directly, or an AGP address? I guess it depends on the AGP etc. register setup. Possibly interesting tidbits from the documentation: About PM4_BUFFER_OFFSET: 'This is a 32MB AGP/PCI pointer to the location of the CCE ring buffer in virtual memory (VM) space (i.e. bit 25 is '1').' (R128_AGP_OFFSET is 0x02000000 == 1 << 25) About PM4_BUFFER_RPTR_ADDR: 'This is a 32MB AGP/PCI pointer to the location of the index of the first unread entry in the CCE buffer. *NOTE*: DL_RPTR must be written via PCI bus mastering.' -- Earthling Michel Dänzer \ Debian (powerpc), XFree86 and DRI developer Software libre enthusiast \ http://svcs.affero.net/rm.php?r=daenzer ------------------------------------------------------- This SF.net email is sponsored by: eBay Get office equipment for less on eBay! http://adfarm.mediaplex.com/ad/ck/711-11697-6916-5 _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
