On Tue, 2003-08-05 at 18:52, Ian Romanick wrote:
Keith Whitwell wrote:
Ian Romanick wrote:
Michel Dänzer wrote:
On Tue, 2003-07-29 at 22:41, Ian Romanick wrote:
1. I don't like the hard-coding of 2*1024*1024 as the size of the indirect buffers. This was copied directly from the R200 driver, but I don't like it. We may want to change the size of this buffer at some point, and hard-coding the value into the client-side driver will make that difficult.
2. I don't like the hackish handing of the pre-1.3 DRM case. Are there other PCI IDs that need the 128MB offset? Do we even support the pre-1.3 DRM anymore? If we don't support the pre-1.3 DRM (and don't intend to fix the support), I'd like to chop all the pre-1.3 stuff out. That will make the Radeon driver "look" a lot more like the R200 driver. That's a good thing IMHO.
Why not always use ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0xffff ) << 16 ) + dri_priv->agpTexOffset
as discussed on IRC? This should work with any chip, memory layout, ...
Here's my inner conflict about that. If there's a perfectly good way to get this value with a simple INREG, why is there an ioctl to get it as well?
Oversight on my part. There are so many spaces that these things can be expressed in, I found one that I knew worked for sure (ie that value in the kernel) and ran with it.
Anyway, is an ioctl really heavier-weight than an INREG?
It probably depends on the platform, I guess. I mis-spoke a bit. The ioctl and the INREG do result in different values. The ioctl gets the base address of the indirect buffers and the INREG gives the base of AGP memory. Either can be used to calculate the base of textures in AGP memory. I think the INREG method is *better*, even for the R200 drivers, because it avoids the hard-coded '+ 2*1024*1024'.
It's sure better than that, but maybe Keith meant RADEON_PARAM_AGP_BASE?
Michel, does that INREG work for PCIGART as well?
No, good point, you need
INREG( RADEON_AIC_LO_ADDR ) + dri_priv->agpTexOffset
for that.
Okay, that would be easy enough to add later. Right now neither driver supports PCIGART texturing. It probably should be added at some point.
In any case, here is what I hope will be the final version of this patch. I have modified the R200 driver to use the same technique to get agp_texture_offset. The required the use of a couple radeon_*.h header files. I hope that's okay. I have tested this on my Radeon 8500 and it works correctly (i.e., gets the same value in agp_texture_offset as the old method).
I'd like to commit this either today or tomorrow.
Index: lib/GL/mesa/src/drv/r200/r200_screen.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/r200/r200_screen.c,v
retrieving revision 1.11
diff -u -d -r1.11 r200_screen.c
--- lib/GL/mesa/src/drv/r200/r200_screen.c 21 May 2003 17:32:08 -0000 1.11
+++ lib/GL/mesa/src/drv/r200/r200_screen.c 7 Aug 2003 19:47:39 -0000
@@ -43,6 +43,8 @@
#include "r200_screen.h"
#include "r200_context.h"
#include "r200_ioctl.h"
+#include "radeon_macros.h"
+#include "radeon_reg.h"
#include "utils.h"
#include "vblank.h"
@@ -127,10 +129,6 @@
return NULL;
}
- screen->agp_texture_offset =
- screen->agp_buffer_offset + 2*1024*1024;
-
-
if (sPriv->drmMinor >= 6) {
gp.param = RADEON_PARAM_AGP_BASE;
gp.value = &screen->agp_base;
@@ -195,6 +193,8 @@
}
if ( !screen->IsPCI ) {
+ unsigned char *RADEONMMIO = screen->mmio.map;
+
screen->agpTextures.handle = dri_priv->agpTexHandle;
screen->agpTextures.size = dri_priv->agpTexMapSize;
if ( drmMap( sPriv->fd,
@@ -208,6 +208,9 @@
__driUtilMessage("%s: IsPCI failed\n", __FUNCTION__);
return NULL;
}
+
+ screen->agp_texture_offset = dri_priv->agpTexOffset
+ + ((INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU) << 16);
}
@@ -234,8 +237,7 @@
screen->logTexGranularity[RADEON_AGP_HEAP] = 0;
} else {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
- screen->texOffset[RADEON_AGP_HEAP] =
- dri_priv->agpTexOffset + R200_AGP_TEX_OFFSET;
+ screen->texOffset[RADEON_AGP_HEAP] = screen->agp_texture_offset;
screen->texSize[RADEON_AGP_HEAP] = dri_priv->agpTexMapSize;
screen->logTexGranularity[RADEON_AGP_HEAP] =
dri_priv->log2AGPTexGran;
@@ -387,10 +389,10 @@
glXGetProcAddress( "__glXEnableExtension" );
if ( glx_enable_extension != NULL ) {
- glx_enable_extension( "GLX_SGI_swap_control", GL_FALSE );
- glx_enable_extension( "GLX_SGI_video_sync", GL_FALSE );
- glx_enable_extension( "GLX_MESA_swap_control", GL_FALSE );
- glx_enable_extension( "GLX_MESA_swap_frame_usage", GL_FALSE );
+ (*glx_enable_extension)( "GLX_SGI_swap_control", GL_FALSE );
+ (*glx_enable_extension)( "GLX_SGI_video_sync", GL_FALSE );
+ (*glx_enable_extension)( "GLX_MESA_swap_control", GL_FALSE );
+ (*glx_enable_extension)( "GLX_MESA_swap_frame_usage", GL_FALSE );
/* Get pointers to libGL's __glXRegisterGLXFunction
Index: lib/GL/mesa/src/drv/r200/r200_reg.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/r200/r200_reg.h,v
retrieving revision 1.6
diff -u -d -r1.6 r200_reg.h
--- lib/GL/mesa/src/drv/r200/r200_reg.h 13 May 2003 21:46:37 -0000 1.6
+++ lib/GL/mesa/src/drv/r200/r200_reg.h 7 Aug 2003 19:47:39 -0000
@@ -1434,11 +1434,5 @@
#define R200_CP_CMD_BITBLT_MULTI 0xC0009B00
#define R200_CP_CMD_TRANS_BITBLT 0xC0009C00
-
-#define R200_AGP_TEX_OFFSET 0x02000000
-
-
-
-
#endif
Index: lib/GL/mesa/src/drv/radeon/radeon_screen.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v
retrieving revision 1.20
diff -u -d -r1.20 radeon_screen.c
--- lib/GL/mesa/src/drv/radeon/radeon_screen.c 21 May 2003 17:32:09 -0000 1.20
+++ lib/GL/mesa/src/drv/radeon/radeon_screen.c 7 Aug 2003 19:47:39 -0000
@@ -112,6 +112,7 @@
ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
+ FREE( screen );
fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_AGP_BUFFER_OFFSET): %d\n",
ret);
return NULL;
}
@@ -165,6 +166,8 @@
}
if ( !screen->IsPCI ) {
+ unsigned char *RADEONMMIO = screen->mmio.map;
+
screen->agpTextures.handle = dri_priv->agpTexHandle;
screen->agpTextures.size = dri_priv->agpTexMapSize;
if ( drmMap( sPriv->fd,
@@ -178,6 +181,9 @@
__driUtilMessage("%s: IsPCI failed\n", __FUNCTION__);
return NULL;
}
+
+ screen->agp_texture_offset = dri_priv->agpTexOffset
+ + ((INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU) << 16);
}
screen->chipset = 0;
@@ -221,8 +227,7 @@
screen->logTexGranularity[RADEON_AGP_HEAP] = 0;
} else {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
- screen->texOffset[RADEON_AGP_HEAP] =
- dri_priv->agpTexOffset + RADEON_AGP_TEX_OFFSET;
+ screen->texOffset[RADEON_AGP_HEAP] = screen->agp_texture_offset;
screen->texSize[RADEON_AGP_HEAP] = dri_priv->agpTexMapSize;
screen->logTexGranularity[RADEON_AGP_HEAP] =
dri_priv->log2AGPTexGran;
@@ -371,10 +376,10 @@
glXGetProcAddress( "__glXEnableExtension" );
if ( glx_enable_extension != NULL ) {
- glx_enable_extension( "GLX_SGI_swap_control", GL_FALSE );
- glx_enable_extension( "GLX_SGI_video_sync", GL_FALSE );
- glx_enable_extension( "GLX_MESA_swap_control", GL_FALSE );
- glx_enable_extension( "GLX_MESA_swap_frame_usage", GL_FALSE );
+ (*glx_enable_extension)( "GLX_SGI_swap_control", GL_FALSE );
+ (*glx_enable_extension)( "GLX_SGI_video_sync", GL_FALSE );
+ (*glx_enable_extension)( "GLX_MESA_swap_control", GL_FALSE );
+ (*glx_enable_extension)( "GLX_MESA_swap_frame_usage", GL_FALSE );
}
}
}
Index: lib/GL/mesa/src/drv/radeon/radeon_screen.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_screen.h,v
retrieving revision 1.14
diff -u -d -r1.14 radeon_screen.h
--- lib/GL/mesa/src/drv/radeon/radeon_screen.h 30 Apr 2003 01:50:52 -0000 1.14
+++ lib/GL/mesa/src/drv/radeon/radeon_screen.h 7 Aug 2003 19:47:39 -0000
@@ -92,6 +92,7 @@
__DRIscreenPrivate *driScreen;
unsigned int sarea_priv_offset;
unsigned int agp_buffer_offset; /* offset in card memory space */
+ unsigned int agp_texture_offset; /* offset in card memory space */
} radeonScreenRec, *radeonScreenPtr;
extern radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv );
Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v
retrieving revision 1.29
diff -u -d -r1.29 radeon_reg.h
--- programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 10 Jun 2003 18:52:57
-0000 1.29
+++ programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 7 Aug 2003 19:47:39
-0000
@@ -1882,8 +1882,6 @@
/* Constants */
-#define RADEON_AGP_TEX_OFFSET 0x02000000
-
#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
