Index: xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h
===================================================================
RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v
retrieving revision 1.15
diff -u -r1.15 radeon_common.h
--- xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h	3 Dec 2003 17:20:24 -0000	1.15
+++ xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h	10 Jan 2004 17:12:32 -0000
@@ -360,7 +360,13 @@
 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
-#define RADEON_MAX_STATE_PACKETS                    76
+#define RADEON_EMIT_PP_CUBIC_FACES_0                76
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             77
+#define RADEON_EMIT_PP_CUBIC_FACES_1                78
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             79
+#define RADEON_EMIT_PP_CUBIC_FACES_2                80
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             81
+#define RADEON_MAX_STATE_PACKETS                    82
 
 
 /* Commands understood by cmd_buffer ioctl.  More can be added but
Index: xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h
===================================================================
RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h,v
retrieving revision 1.25
diff -u -r1.25 radeon.h
--- xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h	16 Dec 2003 07:39:43 -0000	1.25
+++ xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h	10 Jan 2004 17:12:34 -0000
@@ -48,10 +48,10 @@
 
 #define DRIVER_NAME		"radeon"
 #define DRIVER_DESC		"ATI Radeon"
-#define DRIVER_DATE		"20020828"
+#define DRIVER_DATE		"20040105"
 
 #define DRIVER_MAJOR		1
-#define DRIVER_MINOR		10
+#define DRIVER_MINOR		11
 #define DRIVER_PATCHLEVEL	0
 
 /* Interface history:
@@ -84,6 +84,9 @@
  * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
  *       clients use to tell the DRM where they think the framebuffer is 
  *       located in the card's address space
+ * 1.11- Add support for cube map registers on r100:
+ *       RADEON_PP_CUBIC_FACES_[0..2] (RADEON_EMIT_CUBIC_FACES_[0..2])
+ *       RADEON_PP_CUBIC_OFFSET_T[0..2]_0 (RADEON_EMIT_CUBIC_OFFSETS_T[0..2])
  */
 #define DRIVER_IOCTLS							     \
  [DRM_IOCTL_NR(DRM_IOCTL_DMA)]               = { radeon_cp_buffers,  1, 0 }, \
Index: xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h
===================================================================
RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h,v
retrieving revision 1.18
diff -u -r1.18 radeon_drm.h
--- xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h	4 Nov 2003 00:46:05 -0000	1.18
+++ xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h	10 Jan 2004 17:12:35 -0000
@@ -144,7 +144,13 @@
 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
-#define RADEON_MAX_STATE_PACKETS                    76
+#define RADEON_EMIT_PP_CUBIC_FACES_0                76
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             77
+#define RADEON_EMIT_PP_CUBIC_FACES_1                78
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             79
+#define RADEON_EMIT_PP_CUBIC_FACES_2                80
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             81
+#define RADEON_MAX_STATE_PACKETS                    82
 
 
 /* Commands understood by cmd_buffer ioctl.  More can be added but
Index: xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h
===================================================================
RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h,v
retrieving revision 1.24
diff -u -r1.24 radeon_drv.h
--- xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h	16 Dec 2003 08:57:08 -0000	1.24
+++ xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h	10 Jan 2004 17:12:36 -0000
@@ -677,6 +677,12 @@
 #define RADEON_PP_TEX_SIZE_1                0x1d0c
 #define RADEON_PP_TEX_SIZE_2                0x1d14
 
+#define RADEON_PP_CUBIC_FACES_0             0x1d24
+#define RADEON_PP_CUBIC_FACES_1             0x1d28
+#define RADEON_PP_CUBIC_FACES_2             0x1d2c
+#define RADEON_PP_CUBIC_OFFSET_T0_0         0x1dd0  /* bits [31:5] */
+#define RADEON_PP_CUBIC_OFFSET_T1_0         0x1e00
+#define RADEON_PP_CUBIC_OFFSET_T2_0         0x1e14
 
 #define SE_VAP_CNTL__TCL_ENA_MASK                          0x00000001
 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK                   0x00010000
Index: xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c
===================================================================
RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c,v
retrieving revision 1.24
diff -u -r1.24 radeon_state.c
--- xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c	4 Nov 2003 00:46:05 -0000	1.24
+++ xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c	10 Jan 2004 17:12:37 -0000
@@ -110,7 +110,7 @@
 		    id == R200_PP_CUBIC_OFFSET_F1_2 || id == R200_PP_CUBIC_OFFSET_F1_3 ||
 		    id == R200_PP_CUBIC_OFFSET_F1_4 || id == R200_PP_CUBIC_OFFSET_F1_5 ) {
 		int i;
-		for ( i = 0; i < 6; i++ ) {
+		for ( i = 0; i < 5; i++ ) {
 			if ( radeon_check_and_fixup_offset_user( dev_priv,
 								 filp_priv,
 								 &data[i] ) ) {
@@ -118,6 +118,17 @@
 				return DRM_ERR( EINVAL );
 			}
 		}
+	} else if ( id == RADEON_PP_CUBIC_OFFSET_T0_0 || id == RADEON_PP_CUBIC_OFFSET_T1_0 ||
+		    id == RADEON_PP_CUBIC_OFFSET_T2_0 ) {
+		int i;
+		for ( i = 0; i < 5; i++ ) {
+			if ( radeon_check_and_fixup_offset_user( dev_priv,
+								 filp_priv,
+								 &data[i] ) ) {
+				DRM_ERROR( "Invalid R100 cubic texture offset\n" );
+				return DRM_ERR( EINVAL );
+			}
+		}
 	}
 
 	return 0;
@@ -473,7 +484,13 @@
 	{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 	{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
 	{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
-	{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
+	{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+	{ RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
+	{ RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+	{ RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
+	{ RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+	{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
+	{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
 };