Hi Jon,
The problem could be in Radeon memory controller mapping, perhaps
XFree86 from DRI CVS changes it.
You see there is a memory controller on Radeon chip itself which merges
several different address spaces (video ram, AGP and PCI DMA) into one.
The default (when it boots) is such that video ram overlaps the beginning
of PCI DMA space, so you are not able to do DMA into lower 64 or 128 MB of
system RAM.
XFree86 in DRI CVS has the ability to move these address spaces
dynamically.
You might find useful the following piece of code:
int radeon_check_mc_settings(KM_STRUCT *kms)
{
u32 aperture, aperture_size;
u32 mc_fb_location;
u32 mc_agp_location;
u32 new_mc_fb_location;
u32 new_mc_agp_location;
aperture=pci_resource_start(kms->dev,0);
radeon_wait_for_idle(kms);
aperture_size=readl(kms->reg_aperture+RADEON_CONFIG_APER_SIZE);
mc_fb_location=readl(kms->reg_aperture+RADEON_MC_FB_LOCATION);
mc_agp_location=readl(kms->reg_aperture+RADEON_MC_AGP_LOCATION);
new_mc_fb_location=((aperture>>16)&0xffff)|
((aperture+aperture_size-1)&0xffff0000);
if((new_mc_fb_location!=mc_fb_location) ||
((mc_agp_location & 0xffff)!=(((aperture+aperture_size)>>16)&0xffff))){
printk("WARNING ! Radeon memory controller is misconfigured, disabling
capture\n");
printk("WARNING ! upgrade your Xserver and DRM driver\n");
return 0;
}
return 1;
}
it is from GATOS km driver and it checks whether the configuration is the
recommended configuration from ATI docs.
best
Vladimir Dergachev
On Sun, 7 Mar 2004, Jon Smirl wrote:
> I'm trying to merge some of the functions from the radeon DRM and FB device
> drivers into a single driver. I've been working on the code for a week trying to
> get AGP working but I can't seem to figure out what is wrong. In
> drm/radeon_cp.c, radeon_cp_init_ring_buffer() there is a test to see if the GPU
> will write the registers out to AGP space:
>
> RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
> + RADEON_SCRATCH_REG_OFFSET );
> dev_priv->scratch = ((__volatile__ u32 *)
> dev_priv->ring_rptr->handle +
> (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
> RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
> /* Writeback doesn't seem to work everywhere, test it first */
> DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
> RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
> for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
> if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) ==
> 0xdeadbeef )
> break;
> DRM_UDELAY( 1 );
> }
>
> I have tried checking everything in my code and I can't figure out why this
> won't work. I have agp enabled, I bound the memory, I have it mapped in the user
> app and the kernel. I have also checked AGP_COMMAND and the mode is set and AGP
> is enabled. I checked MC_AGP_LOCATION and MC_FB_LOCATION and they look right.
>
> The tricky part is if I run Xfree and then run my code, my code works. So, I
> appear to be missing something in the initial setup. I have tried searching all
> over Xfree but I can't spot the difference.
>
> Does the CP need to be running for this to work?
> Does PCI bus mastering need to be enabled?
> Any other ideas on what to look for?
>
> The code is at bk://mesa3d.bkbits.net/drm. It is kernel 2.6 only and uses sysfs.
> You need the sysfs eeprom driver for ddc to work.
>
>
>
>
> =====
> Jon Smirl
> [EMAIL PROTECTED]
>
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