Also, I've again updated the radeon tiling patch (needs to be applied on top of the mergedfb_pageflip patch), dri patch is the same as before.
http://homepage.hispeed.ch/rscheidegger/dri_experimental/radeon_tiling_dri9.diff
http://homepage.hispeed.ch/rscheidegger/dri_experimental/radeon_tiling_drm10.diff
http://homepage.hispeed.ch/rscheidegger/dri_experimental/radeon_tiling_ddx10.diff
This one fixes a "tiled cursor" problem with not properly aligned resolutions, only enables depth moves if color tiling is enabled, and I've added the option to the man page (staring in disbelief at the macro syntax...).
drm now brute-force-cleans up all surfaces in radeon_do_cleanup.
Roland
Index: radeon_dri.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v retrieving revision 1.11 diff -u -r1.11 radeon_dri.c --- radeon_dri.c 17 Dec 2004 16:50:36 -0000 1.11 +++ radeon_dri.c 25 Jan 2005 16:14:20 -0000 @@ -1328,6 +1282,9 @@ < RADEON_MAX_DRAWABLES ? SAREA_MAX_DRAWABLES : RADEON_MAX_DRAWABLES); + /* kill DRIAdjustFrame. We adjust sarea frame info ourselves to work + correctly with pageflip + mergedfb/color tiling */ + pDRIInfo->wrap.AdjustFrame = NULL; #ifdef PER_CONTEXT_SAREA /* This is only here for testing per-context SAREAs. When used, the Index: radeon_driver.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v retrieving revision 1.36 diff -u -r1.36 radeon_driver.c --- radeon_driver.c 13 Jan 2005 17:35:49 -0000 1.36 +++ radeon_driver.c 25 Jan 2005 16:14:27 -0000 @@ -74,6 +74,7 @@ #define _XF86DRI_SERVER_ #include "radeon_dri.h" #include "radeon_sarea.h" +#include "sarea.h" #endif #include "fb.h" @@ -5347,6 +5450,11 @@ } #endif + if(info->MergedFB) { + /* need this here to fix up sarea values */ + RADEONAdjustFrameMerged(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); + } + info->BlockHandler = pScreen->BlockHandler; pScreen->BlockHandler = RADEONBlockHandler; @@ -6823,12 +7110,10 @@ ? RADEON_CRTC2_V_SYNC_POL : 0)); - /* We must make sure Tiling is disabled. It seem all other fancy - * options in there can be safely disabled too + /* It seems all fancy options apart from pflip can be safely disabled */ save->crtc2_offset = 0; - save->crtc2_offset_cntl = 0; - + save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & RADEON_CRTC_OFFSET_FLIP_CNTL; /* this should be right */ if (info->MergedFB) { @@ -7510,5 +7839,6 @@ #ifdef XF86DRI RADEONSAREAPrivPtr pSAREAPriv; + XF86DRISAREAPtr pSAREA; #endif if (info->showCache && y) { @@ -7543,12 +7903,23 @@ #ifdef XF86DRI if (info->directRenderingEnabled) { - - pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); + /* note cannot use pScrn->pScreen since this is unitialized when called from + RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ + pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); + /* can't get at sarea in a semi-sane way? */ + pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); if (clone || info->IsSecondary) { pSAREAPriv->crtc2_base = Base; } + else { + pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) + % info->CurrentLayout.displayWidth; + pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) + / info->CurrentLayout.displayWidth; + pSAREA->frame.width = pScrn->frameX1 - x + 1; + pSAREA->frame.height = pScrn->frameY1 - y + 1; + } if (pSAREAPriv->pfCurrentPage == 1) { Base += info->backOffset; Index: radeon_reg.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v retrieving revision 1.13 diff -u -r1.13 radeon_reg.h --- radeon_reg.h 12 Dec 2004 02:00:48 -0000 1.13 +++ radeon_reg.h 25 Jan 2005 16:14:30 -0000 @@ -352,6 +352,7 @@ # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) # define RADEON_CRTC_TILE_EN (1 << 15) +# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) #define RADEON_CRTC2_OFFSET_CNTL 0x0328