On Sun, 2005-02-13 at 19:25 -0500, Michel Dänzer wrote: > On Mon, 2005-02-14 at 09:07 +1100, Benjamin Herrenschmidt wrote: > > On Sat, 2005-02-12 at 23:56 -0500, Michel Dänzer wrote: > > > On Sun, 2005-02-13 at 15:16 +1100, Benjamin Herrenschmidt wrote: > > > > > > > > Those are still incorrect as they totally lack memory barriers... > > > > > > INREG() doesn't (or does it?), and it's the only one used by the 3D > > > drivers. > > > > Hrm.. in fact, you are always writing to indirect buffers here, right ? > > > > If this is true, all you need is a barrier between the last store to it > > and whatever store makes the buffer visible to the chip. If you use only > > uncached access (like AGP GART), then only an eieio is necessary, > > Yes, the DRM does this, always has... > > > but if you use PCI GART which works with a cacheable mapping in main > > memory, you probably need a full sync. > > Hasn't seemed necessary all these years.
Because you were lucky enough :) But CPUs like the 970 are much more aggressive with re-ordering of stores and speculation of loads... Ben. ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_ide95&alloc_id396&op=click -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
